Integrated circuit SRAM cell layouts

Details Integrated circuit SRAM cell layouts Integrated circuit SRAM cell layouts

1996-06-07

1998-04-21

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

257206, 257204, 257390, 257908, 257909, H01L 27148, H01L 2710, H01L 2976, H01L 27108

Patent

active

057420785

ABSTRACT:
Integrated circuit SRAM cells include a semiconductor substrate having a field region and first, second, third and fourth active regions therein. The first and second active regions each include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The third and fourth active regions each also include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The integrated circuit SRAM cells also include first and second vertically extending gate conductive layers on the semiconductor substrate. The first vertically extending conductive layer extends vertically over the first active region horizontal leg and extends vertically over the third active region horizontal leg. The second vertically extending conductive layer extends vertically over the second active region horizontal leg and extends vertically over the fourth active region horizontal leg. Accordingly, the gate conductive layers are formed perpendicular to the horizontal legs of the active regions, so that the process alignment margin is large in the longitudinal direction of the active regions. A high integration density may thereby be produced.

REFERENCES:
patent: 5414653 (1995-05-01), Onishi et al.
patent: 5517038 (1996-05-01), Maeda et al.

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