Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2008-04-29
2011-12-20
Gebremariam, Samuel (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257SE23179
Reexamination Certificate
active
08080886
ABSTRACT:
An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.
REFERENCES:
patent: 2004/0102014 (2004-05-01), Ning et al.
Kang Chang-Jin
Kim Myeong-Cheol
Lee Doo-Youl
Lee Si-Hyeung
Ryoo Man-Hyoung
F. Chau & Associates LLC
Gebremariam Samuel
Samsung Electronics Co,. Ltd.
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