Integrated circuit routing and compaction

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

07603644

ABSTRACT:
An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying cells rows and channel, which are gaps between the rows, the technique determines which nets should be routed in which areas. Spine routing is used for nets than span more than one row or channel. Alter the space between rows, larger or smaller, which will allow routing of the nets.

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