Integrated circuit reset circuitry

Details Integrated circuit reset circuitry Integrated circuit reset circuitry

2002-05-29

2004-06-15

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C327S409000, C327S198000

Reexamination Certificate

active

06751139

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and in particular the present invention relates to integrated circuit memory devices.
BACKGROUND OF THE INVENTION
It is desirable to test the operation of integrated circuits during manufacturing. There are numerous ways of testing integrated circuits that reduce test time and expense, as known in the art. One method uses elevated voltages during testing. These elevated voltages are supplied to the device under test on an input connection. As operating speeds increase, the input connections and corresponding circuitry are changing.
In high-speed memory devices, input connection circuits are typically designed to operate at high signal speeds and are performance intensive. These circuits, therefore, are not designed to receive high voltage test signals or supplies. That is, the circuits usually include transistors with thin gate oxide for speed performance and, unlike transistors with thick oxide, cannot sustain higher voltages, such as the elevated test supply voltages
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art to provide voltage supplies during test operations of an integrated circuit.
SUMMARY OF THE INVENTION
The above-mentioned problems with integrated circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a memory device comprises control circuitry to place the memory device in a test mode, and a reset connection to receive an externally provided active low reset signal to reset the memory device. The reset connection can receive an elevated voltage during the test mode. An input buffer circuit is coupled to the reset connection, and a pull-up bias circuit coupled to the reset connection, wherein the pull-up bias circuit is active only during the test mode.
In another embodiment, a synchronous non-volatile memory device comprises an array of non-volatile memory cells, control circuitry to place the memory device in a test mode in response to an external test command, and a supply connection to receive a voltage supply, Vcc. A reset connection is provided to receive an externally provided active low reset signal to reset the memory device. The reset connection can receive an elevated voltage during the test mode, where the elevated voltage is greater than Vcc. An input buffer circuit is coupled to the reset connection, and a pull-up bias circuit coupled to the reset connection, wherein the pull-up bias circuit is active only during the test mode.
A method of operating a memory device comprises initiating a test operation of the memory device, and activating a bias circuit coupled to a reset connection of the memory device during the test operation.
A method of operating a non-volatile memory device comprises initiating a test operation of the memory device via externally provided commands, activating an internal pull-up bias circuit coupled to a reset connection of the memory device, and coupling active low reset signals to the reset connection during a test operation using a first tester. The method includes disconnecting the first tester from the reset connection such that the reset connection is not actively driven from an outside source, wherein the activated pull-up bias circuit prohibits a voltage on the reset connection from transitioning to a low state. An elevated supply voltage is coupled to the reset connection during the test operation, wherein the elevated voltage supply is greater than a memory voltage supply, Vcc.


REFERENCES:
patent: 5159369 (1992-10-01), Hashimoto
patent: 5412264 (1995-05-01), Uda
patent: 5526364 (1996-06-01), Roohparvar
patent: 5561614 (1996-10-01), Revilla et al.
patent: 5569903 (1996-10-01), Matsubara
patent: 5615159 (1997-03-01), Roohparvar
patent: 5636166 (1997-06-01), Roohparvar
patent: 5793775 (1998-08-01), Roohparvar
patent: 5999480 (1999-12-01), Ong et al.
patent: 6246626 (2001-06-01), Roohparvar
patent: 6271675 (2001-08-01), Sakaki
patent: 6278654 (2001-08-01), Roohparvar
patent: 6304497 (2001-10-01), Roohparvar
patent: 6307779 (2001-10-01), Roohparvar
patent: 6314049 (2001-11-01), Roohparvar
patent: 6335648 (2002-01-01), Matsushita
patent: 6442076 (2002-08-01), Roohparvar
patent: 6542427 (2003-04-01), Roohparvar
patent: 2001/0003837 (2001-06-01), Norman et al.
patent: 2002/0075745 (2002-06-01), McLaury
patent: 2002/0129193 (2002-09-01), Roohparvar
patent: 2002/0178414 (2002-11-01), Roohparvar
patent: 2003/0023840 (2003-01-01), Zitlaw et al.
patent: 2003/0046486 (2003-03-01), Zitlaw

Affiliated with

Also associated with

Rating

Integrated circuit reset circuitry does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit reset circuitry, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit reset circuitry will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3365089