Integrated circuit power and ground routing

Details Integrated circuit power and ground routing Integrated circuit power and ground routing

2001-11-09

2004-03-02

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06701509

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to integrated circuits and, more particularly, to the routing of conductors in an integrated circuit to supply power and signals to circuitry therein.
2. Description of the Prior Art
Integrated circuits (“IC's”) include circuitry which is typically organized in a hierarchical fashion of “cells” and “blocks” of cells. Each cell will include a large plurality of circuit elements such as transistors, resistors and capacitors to carry out a particular elementary function. The cells are then grouped into circuit “blocks”, and the IC will have a large number of circuit blocks. IC's use multiple levels of conductors for distributing power and signals from off the IC to the circuit blocks within the IC, between the circuit blocks, and between the cells within each circuit block.
The conductors are formed by lithographically patterning a layer of conductive material to form conductive lines as viewed from above the IC substrate. The conductive layers with conductive lines formed, therein are separated by an insulating layer so that lines of one layer which cross another layer (when viewed from above) do not physically or electrically contact each other. When it is desired to electrically connect a conductor formed in one layer to a conductor formed in another layer, a conductive path is formed extending through the insulating layer between the two conductors. This conductive path is known in the integrated circuit art as a “via”. The conductive layers are typically a metal, most commonly aluminum, but also include tungsten, copper and titanium and various alloys thereof Other materials are also known, such as metal silicides, metal nitrides and doped polysilicon. The insulating layer is commonly a dielectric material such as silicon dioxide.
The layers typically have different resistivities, with the lowest level (layer
1
) having the highest resistivity and the highest level having the lowest resistivity. This is due to technological processing constraints such as smaller thickness at the lower layers. The different resistivities have influenced routing, with the higher resistivity, lower layers generally being used to make connections which are relatively close (e.g. within cells or blocks) while the higher level, lower resistivity layers are used to make longer connections, such as between points in different blocks.
The layout of the conductors has developed to a high degree and various software tools are available to automate the layout process with the input and guidance of the layout engineer. Factors which complicate and affect the layout include the impact of the chosen routing signal propagation with respect to signal timing between various cells and blocks, the impact of the routing on circuit density, and undesirable voltage drops along long conductor runs. The number of conductor layers also affects signal routing. As IC geometries have shrunk, the number.of available layers has increased from three to five, and the number of layers commonly used is expected to further increase.
FIGS. 1-3
illustrate the layout of conductive lines in an integrated circuit employing five conductive layers according to a common approach. For sake of simplicity, and because the conductors need not be limited to metals, the conductive layers in which the conductive lines are formed will be referred to herein as “layer
1
”, “layer
2
”, “layer
3
”, “layer
4
” and “layer
5
”. Layer
1
is closest to the substrate, wit layers
1
,
2
and
3
being referred to as “low level” layers and layers
4
and
5
being referred to as “high level layers”. Individual conductor lines, or simply “conductors”, will bear reference numerals in the form “XYY”, with the digit X corresponding to the layer level in which that conductor resides. i.e. conductor
301
is in layer
3
and conductor
501
is in layer
5
. Additionally, vias will be referred to with the legend “XZYY”, with the digits X and Z referring to the upper and lower, respectively, conductive layers which that via connects.
FIG. 1
is a top view of a standard cell
12
. Within the cell
12
are numerous circuit elements as, discussed above. Along the opposing edges
12
a
,
12
b
of the cell are conductors
101
,
103
lithographically formed from a layer
1
. These horizontally extending conductors, known in the art as “rails”, are used to connect the cell
12
to a source of electric potential vdd! (rail
101
) and to a lower source of potential, such as ground “gnd!” by rail
103
. Connections between individual circuit elements as well as between circuit elements and the respective rail
101
or
103
may also be in layer
1
.
FIG. 2
shows a portion of a “block” of cells. The block
20
includes cells
10
,
11
,
12
,
13
. In practice, a block of cells would typically include many more cells (such as one thousand cells). Generally speaking, each block of cells is “self-contained” in that it has input/output contacts in the form of conductive pads (“pins”) which are connected to other blocks on the IC to electrically connect them together. Additionally, the blocks typically abut each other on all sides to maximize density. Here, the lower row of cells
10
,
11
is bounded by another rail
105
, in this case a power rail. Also shown, are conductors
202
,
204
,
206
,
208
extending orthogonal to the rails
101
,
103
and
105
and formed from a conductive layer
2
in a plane above and parallel to the layer
1
from which the rails
101
-
105
were formed. The conductors
202
,
204
,
206
,
208
are known in the art as “stripes” and alternate in a similar manner as the rails with respect to connection to power (vdd!) and ground (gnd!). The ground stripes
204
,
208
are connected to ground rail
103
by respective vias
2101
and
2102
. The power stripes
202
,
206
are connected to the power rails
101
,
103
by respective vias
2103
,
2104
,
2105
,
2106
.
Typically, in a five layer system, the interconnection between blocks for signal routing is done in layer
5
. Additionally, the power and ground conductors which distribute power across the IC from an off chip source of potential to the various blocks of cells are also in layer
5
. The supply of power to the blocks, the supply of signals to and from the blocks, and the supply of signals between the blocks is known as the “top-level” design. Power and ground conductors at the cell level are in layer
1
while power and ground connections at the block level are in layers
2
,
3
, as illustrated in FIG.
2
. Signal routing within a block is done in layers
3
,
4
. (not shown).
The layout design of an IC is typically done in a hierarchical fashion, starting from the cell level, moving to the block level and then the top level. The blocks are conventionally designed by a plurality of designers using the same software layout tools in a parallel fashion. When the block layouts are completed, the top level layout is then designed.
One problem with this layout approach of using conductors in layer
2
for power and ground delivery at the block level is that this allows access to the contact pins of each cell for from layer
1
only. Use of layer
1
for signal routing over anything more than very short distances makes it difficult to achieve proper signal timing because of its high resistivity. Cells cannot be placed under the layer
2
stripes
202
,
204
,
206
,
208
of
FIG. 2
, because doing so would require the use of metal
1
for signal routing.
FIG. 3
is a view of the area of block
20
around the stripes
202
,
204
. Instead of showing only four cells as in
FIG. 2
,
FIG. 3
illustrates many more cells arranged in rows R
1
-RN. Under the stripes
202
,
204
it is quite evident that there is significant chip area under these stripes which does not contain cells. This wasted space thus reduces the circuit density of the IC and increases its cost.
Conventionally, vias extend only vertically between layers, i.e. orthogonal to the stripes and rails. This poses

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