Integrated circuit planarizing process

Details Integrated circuit planarizing process Integrated circuit planarizing process

1982-04-28

1985-06-18

Lawrence, Evan K.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156657, 1566611, 156668, H01L 21312

Patent

active

045239754

ABSTRACT:
A planarizing process for producing a passivation or insulating layer immediately underlying an upper metallized layer on the surface of an integrated circuit having very large radius of curvature steps, thus providing a reliable base for the metallized layer. The process is comprised of the steps of depositing and defining first metal conductors on the surface of an integrated circuit, depositing a first dielectric layer over the surface of the integrated circuit including the conductors, the dielectric layer being comprised of material selected from the group comprised of silicon dioxide and silicon nitride, depositing and polymerizing a layer of negative isoprene resist over the surface of the dielectric layer, plasma etching the surface of the isoprene and dielectric layers to a predetermined thickness over the metal conductors in an atmosphere of CF.sub.4 gas containing 32 to 50% oxygen, cleaning the etched surface, and depositing a second dielectric layer over the surface selected from a group comprised of silicon dioxide and silicon nitride, whereby a surface having very large radius of curvature steps over the metal conductors is produced.

REFERENCES:
patent: 4025411 (1977-05-01), Hom-Ma et al.
patent: 4070501 (1978-01-01), Corbin et al.
patent: 4321284 (1982-03-01), Yakushiji

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