Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1995-07-13
1999-03-16
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438622, 438624, 438760, 438782, 438784, 438958, H01L 21268
Patent
active
058830014
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit passivation structures and processes, and more particularly to a passivation process and structure adapted for UV erase EPROMs.
2. Description of Related Art
An integrated circuit passivation layer coats the device with a protective covering. The protective covering performs a number of functions, including protecting the device from stress which may occur during package molding or otherwise, and protecting the device from contamination and moisture in the environment. Thus, passivation structures should be resistant to thermal and mechanical stress, non-porous to mobile ions which may appear on the surface of the device particularly in moist conditions, and electrical insulating. For some devices, which include UV erase EPROM cells, the passivation layer must also be transmissive to the ultraviolet radiation.
The passivation layer, in addition to providing a protective coating for the device, must be opened over contact pads formed on the device. The contact pads are used for connecting wiring in the package to the metal layers on the integrated circuit. Thus, the passivation process must support a technique for making openings in the passivation layer to expose contact pads.
All of these features have led to significant development in the field of passivation layers for integrated circuits. The following U.S. Patents provide background information for the present invention: U.S. Pat. No. 4,581,622 entitled UV ERASABLE EPROM WITH UV TRANSPARENT SILICON OXYNITRIDE COATING; U.S. Pat. No. 5, 260,236 entitled UV TRANSPARENT OXYNITRIDE DEPOSITION IN SINGLE WAFER PECVD SYSTEM; U.S. Pat. No. 5,010,024 entitled PASSIVATION FOR INTEGRATED CIRCUIT STRUCTURES; U.S. Pat. No. 4,618,541 entitled METHOD OF FORMING SILICON NITRIDE FILM TRANSPARENT TO ULTRAVIOLET RADIATION AND RESULTING ARTICLE; U.S. Pat. No. 5,306,946 entitled SEMI-CONDUCTOR DEVICE HAVING A PASSIVATION LAYER WITH SILICON NITRIDE LAYERS; U.S. Pat. No. 4,665,426 entitled EPROM WITH ULTRAVIOLET RADIATION TRANSPARENT SILICON NITRIDE PASSIVATION LAYER; and U.S. Pat. No. 4,986,878 entitled PROCESS FOR IMPROVED PLANARIZATION OF THE PASSIVE LAYERS FOR SEMI-CONDUCTOR DEVICES.
Notwithstanding substantial development in the art of passivation layers, it is desirable to provide an improved structure. Particularly, it is desirable to provide a passivation structure and process which can completely fill the voids in underlying structures as the design rules for integrated circuits shrink, which provides protection against moisture and mobile ion penetration, which involves a process which does not degrade device reliability, which has high UV light transparency for efficient UV erase of EPROM cells, and which is cost-effective and manufacture worthy.
SUMMARY OF THE INVENTION
The present invention achieves the goals stated above for providing a improved passivation process and coating. It can be characterized as a method for forming a passivation coating on an integrated circuit, after completion of the active device and metal routing circuitry. These precursor processes result in an integrated circuit having a non-planar features, and at least one conductive pad for providing connection to the packaging. The method comprises the following steps: dielectric over the first dielectric layer; second dielectric coating, and defining an opening in the protective pattern layer over the at least one conductive pad; exposed by the opening; through the opening, including the remaining portions of the second dielectric layer, the flowable dielectric layer and the first dielectric layer, down to the conductive pad; and composed of silicon oxynitride, is deposited using a plasma enhanced chemical vapor deposition to form a dielectric layer resistant to mobile ion penetration, and having high quality.
The step of smoothing out the underlying features is accomplished by spin coating and curing a flowable glass over the first dielectric layer to smooth out the underlying feat
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Chang Chung Chi
Chang Po Shen
Hwang Gino
Hwang Wen Yen
Jin Been Yih
Bowers Charles
Haynes Mark A.
Macronix International Co. Ltd.
Nguyen Thanh
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