Integrated circuit package with solder bumps

Details Integrated circuit package with solder bumps Integrated circuit package with solder bumps

2002-12-18

2004-06-15

Vigushin, John B. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

C257S707000, C257S778000

Reexamination Certificate

active

06750552

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor packaging, in particular semiconductor packaging techniques using solder bumps or studs.
BACKGROUND
Evolving end-use applications for electronic components dictate smaller and faster, yet reliable components. Cellular phones, video cameras, laptop computers and personal digital assistants are examples of products that are more attractive if they are smaller, yet have superior performance and reliability. These end-use applications require semiconductor chips, or integrated circuit (“IC”) packages, that have reduced size and increased input/output (“I/O”) density. To be acceptable for most end-use applications, these chips must also have a reasonably long life in conditions that include thermal cycling in a close environment and shock, such as from accidental dropping. Traditional wirebond technologies do not provide the size, electrical performance, and reliability required by most modern high performance ICs. Several alternatives to wirebond technology have been developed to respond to the challenges presented by modern electronic end-use applications. For example, flip-chip technology positions the semiconductor die (typically formed on a silicon base) on top of the substrate and bonds the die to the substrate with a series of solder bumps or alternatively, studs. The solder bumps typically include both “active” and “dummy” bumps. Active bumps serve as signal paths for the IC. Dummy bumps are for mechanical bonding.
Similar technologies to flip-chip packages are ball grid array packages and chip scale packages (“CSPs”), all of which place the die on top of the substrate. Typically, these packages are attractive because they allow high I/O density and have good heat dissipation characteristics. One requirement for reliability is that the solder bumps maintain the bond between the die and the substrate. If active bumps break, the IC can fail. If a dummy bump fails, mechanical instability can be introduced, eventually leading to other failures. The likelihood of bump failure increases as the distance from the center point of the die (known as the distance from the neutral point, or “DNP”) increases. The relationship between the size of the die and the size of the substrate also affects IC life. For example, for the same die size, the number of temperature cycles before failure is greater for relatively larger substrates. The IC design process, therefore, takes into consideration the aspect ratio of the die, the placement of both active and dummy bumps, and the relative sizes of the die and the substrate.
Typical IC packages using dummy bumps have die with low aspect ratios. For example, for a common flip-chip package, the maximum ratio of die length to die Width (i.e., the aspect ratio) is marginally greater than 1.0 and less than 1.3. For some applications, however, die with significantly higher die aspect ratios are desired or required. As die aspect ratio increases for a fixed die surface area, DNP increases even though surface area does not.
FIG. 1
illustrates this by showing a hypothetical die
102
and a hypothetical die
104
with identical surface areas. Die
102
has an aspect ratio of 1, while die
104
has an aspect ratio of 4. The die
102
has an approximate maximum DNP
103
. The die
104
has an approximate maximum DNP
105
. It is evident that the DNP
105
(approximately 2.1) is greater than the DNP
103
(approximately 1.4). Current design practices may be inadequate to produce a reliable IC given a die with a relatively high aspect ratio. For example, merely trying to place active bumps further from the periphery of the die may still place active bumps on the long axis of the die with a DNP that is too great to guarantee acceptable reliability.
Thus, there is a need for an integrated circuit semiconductor package and a method for fabricating the same that provides acceptable performance and reliability given a semiconductor die with a relatively high aspect ratio.


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patent: 5744859 (1998-04-01), Ouchida
patent: 6462420 (2002-10-01), Hikita et al.
patent: 2001/0009302 (2001-07-01), Murayama et al.
patent: 01238148 (1989-09-01), None

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