Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2000-10-10
2003-06-24
Fahmy, Jr., Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S678000, C257S779000, C257S780000
Reexamination Certificate
active
06583513
ABSTRACT:
This invention relates generally to integrated circuit packages. In particular, the invention relates to an improved integrated circuit package which includes an integrated circuit chip and provides electrical interconnections between the integrated circuit chip and a circuit board, card or other substrate on which the integrated circuit package may be disposed.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) are used in most categories of technological products embracing both commercial and military applications. Traditionally, a silicon chip die or integrated circuit chip is electrically coupled to a package substrate using wire bonding between output pads located around the periphery of the die and conductive traces on the package. As the number of interconnections to integrated circuit (IC) chips increases, forming the required number of output pads around the chip periphery becomes impractical.
One solution which provides increased output pad density is the “flip chip” package. The flip chip package has an area array configuration in which the active side of the chip die includes an array of output pads. A passivation layer coated on the active surface of the chip die around the output pads protects the chip's active components from environmental contaminants. Instead of electrically coupling the chip or die to the package substrate using traditional wire bonding techniques, solder bumps are formed on the array of output pads of the chip. The solder bumps are approximately spherically-shaped solidified solder and are typically of a tin-lead composition. The chip is flipped so that its solder bumps are positioned or aligned in registering contact to a connecting pattern of conductive traces formed on a package substrate. The temperature is then increased to cause the solder bumps to reflow for direct electrical and mechanical bonding of the output pads of the chip to contact sites on the package substrate.
The wire bonding and the solder bump techniques outlined above are both used to create primary interconnects between the IC chip and the IC package substrate.
Coupling of the integrated circuit package to a circuit board, card or other suitable substrate using secondary interconnects may be achieved in a number of ways. Commonly used secondary interconnections include, for example, peripheral leads (as found in quad flat packages), pin grid arrays, ball grid arrays, and socket connections.
U.S. Pat. No. 5,798,567, assigned to Hewlett-Packard, discloses in the prior art section a typical quad flat package and a typical ball grid array (BGA) package. The inventive embodiment of U.S. Pat. No. 5,798,567 show an IC package with primary interconnects in the form of solder bumps which electrically couple the chip die to the BGA substrate. Secondary interconnects are provided by a set of relatively large solder balls which electrically interconnect the BGA substrate to a circuit board. Power supply vias, ground vias, and electrically conductive traces interconnect the solder bumps to the larger solder balls.
To improve device reliability the chip die is usually insulated from the environment and from mechanical stresses by surrounding the die with a sealed lid or an overmold compound.
Semiconductor chip dice, like other electronic devices, generate heat during operation. This generated heat must be dispersed from the die to ensure that the temperature of the chip remains within an optimum operating range. Heat dispersion techniques are therefore an important consideration in the design of a semiconductor package.
A drawback with “flip chip” package designs is that heat dissipation is relatively low compared to other chip packages such as wire-bonded packages. Furthermore, as the number and density of output pads increases in the “flip chip” package, the rate of heat generation tends to increase leading to an escalation of the heat dissipation problem. There is thus a need for increasingly efficient heat dispersion techniques for use in “flip chip” packages to ensure the chip die operates effectively.
SUMMARY OF THE INVENTION
The present invention provides an integrated circuit package including an integrated circuit chip or die with a plurality of pads (which can include pads used for input/output signals, power supply, and/or grounding) coupled to a set of primary interconnects or conductors. A first subset of the pads is used for interconnection purposes whilst a second subset of the pads is employed purely to disperse heat away from the chip (the electrical interconnects can also be used for heat dispersion). In this way, the chip can be maintained at an optimum temperature during operation.
According to a first aspect of the present invention there is provided an integrated circuit package comprising: a substrate; a chip die; a plurality of pads carried by the chip die, a first subset of the pads in electrical communication with circuitry in the chip die and a second subset of the pads in thermal communication with the chip die; a plurality of external interconnects carried by the substrate; a plurality of electrical conductors for carrying electrical signals between the external interconnects and the first subset of pads; and a plurality of thermal conductors for carrying heat from the second subset of pads to the substrate.
According to a second aspect of the present invention there is provided an integrated circuit package comprising; a planar substrate having first and second major surfaces and a plurality of electrically conductive traces, a chip die mounted on the first major surface of the substrate, the chip die having a plurality of output pads, a set of primary interconnects arranged to couple the output pads of the chip die to the electrically conductive traces of the substrate, and a set of secondary interconnects arranged to couple the electrically conductive traces to external circuitry, wherein a first subset of the primary interconnects are electrically coupled using the electrically conductive traces to the secondary interconnects, such that the output pads associated with the first subset of the primary interconnects function as electrically interconnecting pads, and a second subset of the primary interconnects are thermally coupled using thermal vias to the second major surface of the substrate, such that the output pads associated with the second subset of the primary interconnects function as non-electrically interconnecting thermal-dissipation pads.
An integrated circuit package in accordance with the invention has the advantage that during operation, heat may be drawn away from the chip through dedicated thermal-dissipation pads which can be coupled using standard techniques to a set of dedicated thermal primary interconnects or conductors. Thermal vias may be employed to provide a thermal path from the second subset of primary interconnects to the opposite side of the package substrate. Thus, the package is able to efficiently disperse heat from the chip in a simple and effective manner.
REFERENCES:
patent: 5798567 (1998-08-01), Kelly
patent: 5889324 (1999-03-01), Suzuki
patent: 5939783 (1999-08-01), Laine et al.
patent: 6046499 (2000-04-01), Yano
patent: 6140707 (2000-10-01), Plepys et al.
patent: 6154366 (2000-11-01), Ma et al.
patent: 6204562 (2001-03-01), Ho
patent: 6277672 (2001-08-01), Ho
patent: 6291893 (2001-09-01), Tiziani
patent: 6380620 (2002-04-01), Suminoe et al.
patent: 6384485 (2002-05-01), Matsushima
patent: 6396145 (2002-05-01), Nagai et al.
patent: 6479903 (2002-11-01), Briar
patent: 406216284 (1994-08-01), None
Chong Num-Kwee
Utagikar Ajit
Fahmy Jr. Wael
Ha Nathan W.
LandOfFree
Integrated circuit package with an IC chip and pads that... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit package with an IC chip and pads that..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit package with an IC chip and pads that... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3119455