Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-01-19
2002-10-15
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S776000, C257S784000
Reexamination Certificate
active
06465891
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit packaging technology, and more particularly, to an integrated-circuit package with a quick-to-count finger layout design on substrate, which can help fabrication engineers to visually count the total number of electrically-connecting fingers on the substrate in a quick and accurate manner.
2. Description of Related Art
An integrated-circuit package is typically constructed of a semiconductor chip mounted over a substrate. To allow external connections, the substrate is formed with a plurality of electrically-conductive bond pads, commonly called “fingers”, which are arranged around the semiconductor chip. During wire-bonding process, these fingers are bonded by means of a plurality of electrically-conductive wires, such as gold wires, to the respective bond pads on the semiconductor chip.
FIG. 1
shows a schematic plan view of an integrated-circuit package with a conventional finger layout design on substrate. As shown, the integrated-circuit package includes: (a) a substrate
100
; (b) a semiconductor chip
110
mounted over the substrate
100
, and whose top surface is formed with a plurality of bond pads
111
; (c) a line-up array of fingers
120
surrounding the semiconductor chip
110
; and (d) a plurality of bonding wires
130
for connecting the bond pads
111
respectively to the fingers
120
(note that
FIG. 1
is a simplified schematic diagram showing only those parts that are related to the invention; the actual layout on the substrate
100
may be much more complex).
By the conventional finger layout design, the line-up array of fingers
120
are all identically-shaped and equally sized, so that their outer appearances are virtually undistinguishable from each other.
During the packaging process, as the wire-bonding step is completed, the fabrication engineers need to check the wire-bonded fingers
120
for the total number thereof This task is customarily carried out by visually inspecting the fingers
120
and mentally counting the total number thereof
However, since today's advanced technology are making the package size extremely small with high packing density, the fingers
120
are typically made very small in size and arranged in very close proximity to each other; and therefore, it would be highly difficult to quickly and accurately check the total number of the fingers
120
through visual inspection and mental counting by the fabrication engineers. The results would therefore highly untrustworthy.
Related patents, include, for example, the U.S. Pat. No. 5,898,213 entitled “SEMICONDUCTOR PACKAGE BOND POST CONFIGURATION”. This patent teaches the use of a staggered finger layout design to reduce finger pitch for compact design of the package size. However, the use of this patent would still make it highly difficult to quickly and accurately check the total number of the fingers through visual inspection and mental counting by the fabrication engineers.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide an integrated-circuit package with a quick-to-count finger layout design on substrate, which can help fabrication engineers to count the total number of the fingers on the substrate more quickly and accurately than the prior art.
In accordance with the foregoing and other objectives, the invention proposes an integrated-circuit package with a quick-to-count finger layout design on substrate.
Broadly recited, the integrated-circuit package with a quick-to-count finger layout design according to the invention comprises the following components: (a) a substrate; (b) a line-up finger array over the substrate, the line-up finger array including: (b1) a plurality of first-shape fingers partitioned equally in number into a plurality of subgroups, each subgroup containing a predetermined number of the first-shape fingers; and (b2) a plurality of second-shape fingers, which are substantially visually distinguishable in outer appearance from the first-shape fingers, and which are interposed between adjacent subgroups of the first-shape fingers to serve as count tokens; and (c) a semiconductor chip mounted over the substrate and wire-bonded to the first-shape fingers and second-shape fingers over the substrate.
To allow the second-shape fingers, which serve as count tokens, to be visually distinguishable from the first-shape fingers, feasible layout design schemes include the use of two different sizes, shapes, and colors respectively for the second-shape fingers and the first-shape fingers. The fabrication engineers can count the total number of the line-up array of fingers on the substrate simply by counting the total number of the second-shape fingers and then multiply the result by the total number of first-shape fingers in each subgroup plus one. Compared to the prior art, it is apparent that the invention allows the fabrication engineers to count the total number of the fingers on the substrate more easily and accurately.
REFERENCES:
patent: 5898213 (1999-04-01), Torres et al.
Liao Chih-Chin
Wang Wen-Hsin
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Siliconware Precision Industries Co. Ltd.
Talbott David L.
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