Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2000-03-02
2002-10-08
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S778000, C257S779000, C257S780000, C257S781000, C257S786000, C228S180220, C361S768000, C361S772000
Reexamination Certificate
active
06462414
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of integrated circuit substrates and packaging and more specifically to methods and devices which improve the reliability of conductive ball joints, especially when mounted on a printed circuit board.
Integrated circuits (ICs) or “chips” are becoming denser and are providing higher performance and functionality per unit area. Many ICs have hundreds of pads that will interface with the printed circuit board (PCB). The packaging for the IC seals the chip and connects the pads of the chip to the balls, pins, leads, or other electrical contacts of the package.
It is important that the IC package is relatively low in cost. Previous generations of IC packages were ceramic or included materials or used techniques that increased the cost of the packaging. It is also important that the IC packaging sufficiently protects the chip and provides the necessary number of electrical connections, and provides this function, using as small a package size as possible. A package with a smaller footprint takes up less PCB space and more ICs can be mounted on a single PCB.
Another important consideration in ICs packaging is reliability. One concern is that when an IC package is soldered or otherwise electrically connected to the PCB, the IC package should be reliably electrically connected to the PCB, or else over time open circuit or no connection failures will result. Because temperature cycling occurs when the IC heats up during operation, and cools off when not in operation, the solder connections between the IC and the PCB may be subjected to shear and stress forces as the package expands and contracts. The solder balls may work harden and then fracture. Consequently, cracks in the solder balls will cause open circuits, and ultimately system failure.
Therefore, as can be appreciated, methods and devices are needed to provide IC packaging with a lower cost, smaller package size, and better reliability. Specifically, there is a need to design integrated circuit packages which enhance solder ball reliability and longevity while maintain the small size of the package and large amount of contacts between the die and the PCB.
SUMMARY OF THE INVENTION
The present invention provides electronic devices, integrated circuit packages, and substrates having an improved conductive ball land area. The ball land area has a locking structure that improves the ball joint by interlocking the conductive ball lead to the land area on a substrate of the integrated circuit package. In one implementation, the locking structure is a conductive material added to the surface of the ball pad to provide a nonplanar or discontinuous interface, such as a dome or a step, which interlocks the conductive ball to the ball pad. “Nonplanar” is used throughout the specification to mean that the interface has more than minor surface variations and that the nonplanar interface substantially increases the area of contact, moves the shear plane to a higher and larger portion on the conductive ball, and/or prevents a crack from propagating along a flat plane across the ball joint, such that the nonplanar surface slows the movement of a crack across the conductive ball. This package construction maintains the small size of the ball land areas and the package, and increases the life of the integrated circuit package, while offsetting the problem of package warpage.
In one aspect, the present invention provides a substrate. The substrate has a dielectric layer having a via which extends between a first surface and a second surface of the dielectric layer. A conductive ball pad is positioned to permit electrical coupling through the via. A second portion of the conductive ball pad defines a nonplanar interface for a conductive ball and extends through the via toward a plane of the first surface.
In another aspect, the present invention provides a semiconductor package. The package includes a dielectric layer having a via which extends between a first surface and a second surface. A conductive pad is coupled to the second surface of the dielectric layer and is positioned to permit electrical coupling between a conductive lead and the conductive pad. A conductive structure is disposed over at least a portion of the conductive pad. An exposed surface of the conductive structure and any exposed surface of the conductive pad define a nonplanar interface which engages and interlocks the conductive lead. The nonplanar interface has a larger surface area than the area of the conductive pad.
In another aspect, the present invention provides a system for coupling an integrated circuit package to a printed circuit board. The system includes a conductive ball and a ball land area disposed on a substrate on the integrated circuit package. The substrate has a dielectric layer having a first surface, a second surface, a thickness extending between the first surface and the second surface, and a via that extends from the first surface to the second surface. A conductive layer is coupled to the second surface of the dielectric layer such that the via exposes a conductive ball pad of the conductive layer which permits electrical and mechanical coupling to the conductive ball. A plated up structure is disposed on the conductive ball pad and extends into the via. The plated up structure increases the shear strength of the interface by moving the shear plane to a larger portion of the conductive ball.
In yet another aspect, the present invention provides a method. The method includes the steps of providing a dielectric layer having a via. A portion of a conductive layer is exposed through the via in the dielectric layer. A conductive structure is added on the conductive layer to create a nonplanar interface which is exposed through the via.
In another aspect, the present invention provides a method of engaging a conductive lead. The method includes the steps of defining a land area on a substrate. A material is added to the land area to create a nonplanar interface between the conductive lead and the land area.
In yet another aspect, the present invention provides a method of fabricating a substrate. The method includes the steps of adding a conductive structure to a surface of a ball pad. A coating of photoresist is applied to the conductive structure. A desired portion of the photoresist is masked and the photoresist is exposed to a light source. Portions of the photoresist will be exposed to light and other portions will not be. Unwanted portion of the photoresist can be removed. The unwanted portion of the conductive structure underneath the removed photoresist is etched away and the remaining photoresist is removed.
In still another aspect, the present invention provides a method having the steps of providing a dielectric material having a via which exposes a ball bonding pad. A nonplanar conductive locking structure is then formed at the bonding pad. A conductive ball coupled to the ball bonding pad without the locking structure defines a shear plane, and the conductive ball coupled to the ball bonding pad having the nonplanar locking structure defines a shear interface which has a larger area than the shear plane.
In yet another aspect, the present invention provides a method having the steps of providing a printed circuit board and an integrated circuit having a ball bond pad which has a conductive ball locking structure with an exposed surface which limits the movement of a fatigue crack across the interface between the ball bond pad and a conductive ball. A conductive ball is interlocked between the printed circuit board and the integrated circuit.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.
REFERENCES:
patent: 3462349 (1969-08-01), Gorgenyi
patent: 3541222 (1970-11-01), Parks et al.
patent: 4652336 (1987-03-01), Andrascek et al.
patent: 4830264 (1989-05-01), Bitaill
Altera Corporation
Chambliss Alonzo
Talbott David L.
Townsend and Townsend / and Crew LLP
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