Integrated circuit package substrate integrating with...

Details Integrated circuit package substrate integrating with... Integrated circuit package substrate integrating with...

2000-12-19

2002-08-06

Martin, David S. (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S761000, C361S830000, C361S734000, C361S738000, C174S266000, C174S265000

Reexamination Certificate

active

06430059

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to an integrated circuit package substrate. More particularly, this invention relates to an integrated circuit package substrate integrating with a decoupling capacitor.
2. Description of the Related Art
Due to the great demand of high density, high integration, multi-function, high performance of integrated circuit package, the semiconductor chip has approached the deep sub-micron regime, and various kinds of high density integrated circuit packages have been developed. For example, the chip scale package (CSP), the multi-chip module (MCM) and the wafer level package have been developed and widely applied in integrated circuit package. The laminated board is made of alternate lamination of multi-layers of patterned wiring layers and insulating layers. As complex and delicate circuits can be formed within the laminated board, it has been commonly used as the carrier for package with high pin counts or high density in the industry of integrated circuit packages.
In
FIG. 1
, a cross sectional view of a conventional integrated circuit package substrate is shown. The conventional integrated circuit package substrate comprises a laminated board which is laminated by the patterned wiring layers
104
a
,
104
b
,
104
c
,
104
d
and the insulating layers
102
. Between every two patterned wiring layers
104
a
to
104
d
, an insulating layer
102
is inserted for isolation. The patterned wiring layers
104
a
to
104
b
can be formed by performing photolithography and etching process on a copper coil. The insulating layers
102
are made of glass epoxy such as FR-4, FR-5, bismaleimidetriazine (BT) or epoxy. Several vias
106
are forming through the insulating layers
102
to electrically connect the patterned wiring layers
104
a
to
104
c
. The patterned wiring layer
104
d
on the top surface of the laminated board
100
is patterned into several mounting pad or gold finger
108
as the terminals for connecting a chip. The mounting pads
108
are normally coated with a gold layer
110
. Similarly, the patterned wiring layer
104
at on the bottom surface of the laminated board
100
are also patterned into several terminals
114
such as the ball pads of a ball grid array (BGA). Again, these ball pads are normally coated with a gold layer
116
. A solder mask layer
112
is formed on both the top and bottom surfaces of the laminated board
100
to cover the patterned wiring layers
104
a
and
104
b
, except that the mounting
108
pads and the ball pads
114
are exposed.
For those integrated circuit packages applied to high pin count integrated circuit devices, that is, the devices with many input/output signals and versatile functions such as the bus south bridge, north bridge, accelerated graphics port (AGP) in the computer, a very high electrical performance is demanded. Therefore, a high performance in signal transmission and effective noise elimination are required. In the conventional, structure, one or more decoupling capacitors are added between the power source and the ground to achieve such requirements.
However, by adding the decoupling capacitor between the power source and ground has the following drawbacks:
1. The noise of input/output signal cannot be eliminated.
2. A signal interference is caused by the power and ground bounce between the power source and ground.
3. A signal degradation is easily resulted.
4. Too much excessive gate propagation delay is caused.
5. A malfunction of the system is resulted due to false triggering.
The above drawbacks greatly degrade the performance of the integrated circuits.
There are two ways to improve the electrical characteristics using decoupling capacitors. That is, the decoupling capacitors are disposed in the main board to electrically connect the integrated circuit, or the decoupling capacitors are formed on the package substrate using surface mount technology (SMT) to electrically connect the integrated circuit. Both of these two methods have the natures of high cost, mutual inductance, limitation on capacitor location, occupancy of large area and requirement of SMT for assembling IC package.
SUMMARY OF THE INVENTION
The invention provides an integrated circuit package substrate that integrates with a decoupling capacitor to reduce the noise and signal attenuation, so that the electrical performance can be improved.
The invention provides a laminated board used as an integrated circuit package substrate. The laminated board comprises a plurality of patterned wiring layers alternatively laminated with a plurality of insulating layers. A plurality of vias are formed to penetrate through at least one of the insulating layers to electrically connected the patterned wiring layers insulated by the insulating layers. A capacitor is formed penetrating through the insulating layers. The capacitor further comprises two electrodes, formed at two opposite sides and a dielectric layer formed between the electrodes. One of the electrode is connected to the power source, while the other electrode is connected to ground.
Thus constructed, the invention includes comprises at least the following advantages:
1. The integrated circuit package substrate integrates with a decoupling capacitor, so that the noise and signal attenuation can be minimized, the bouncing signal surge between the power source and the ground and additional transmission delay by can be eliminated. Therefore, the faulty operation caused by the bouncing signal can thus be avoided.
2. As the decoupling capacitor is integrated within the substrate (the laminated board) to avoid the multiple module design. The occupied area can thus be save to reduce the cost and enhance the design and flexibility in design. The overall electrically performance is consequently improved.
3. By integrating the decoupling capacitor, the voltage dropped caused by high frequency can be led to ground without affecting the loading. The harmonic wave component can be greatly reduced. In addition, it can also function as a bypass current can be added between the power source and ground to shorten circuit path of the transient current.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 4921054 (1990-05-01), Voss et al.
patent: 5384434 (1995-01-01), Mandai et al.
patent: 5404044 (1995-04-01), Booth et al.
patent: 6005197 (1999-12-01), Kola
patent: 6121554 (2000-09-01), Kamikawa
patent: 6153290 (2000-11-01), Sunahara
patent: 2329073 (1999-03-01), None

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