Integrated circuit package architecture with a variable...

Details Integrated circuit package architecture with a variable... Integrated circuit package architecture with a variable...

1998-03-25

2001-03-13

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S123000, C438S127000

Reexamination Certificate

active

06200828

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 86116975, filed Nov. 14, 1997, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit (IC) manufacture technologies, and more particularly, to a new IC package architecture with a variable dispensed compound and a method of manufacturing the same. With this IC package architecture, the dispensed compound can be formed from a suitably selected material by the manufacturer in accordance with actual application requirements.
2. Description of Related Art
Integrated circuits are widely used in computers and intelligent electronic devices. Since IC chips are very small in size, they are usually supplied in packages for easy handling and utilization. The manufacture of ICs involves very complicated processes which can involve several hundreds of steps and needs several months to complete. The semiconductor industry is composed of four major branches: IC design, wafer fabrication, wafer testing, and packaging, each being a highly specialized field which requires state-of-the-art technologies and large amounts of capitals to accomplish.
The manufacture of an IC package includes three essential steps: preparing a wafer, forming a predesigned circuit on the wafer, and finally packing each die (chip) cutting apart from the wafer in a package. The packaging process is the final stage in the IC manufacture.
Conventional packaging methods, however, only involve one single molding process to form a molded compound for enclosing the chip therein. In some IC products where the enclosed chips should be transparent to the outside, such as EPROM (erasable programmable read-only memory) and EEPROM (electrically erasable programmable read-only memory), the molding is performed by using relatively expensive materials, such as ceramic, to form the compound. The manufacturing cost is therefore very high. Moreover, the conventional packaging methods will not allow the compound to be variably formed with a selected color for identification purpose of the integrated circuit.
FIGS. 1A-1C
are schematic sectional diagrams used to depict the architecture of a conventional IC package and the steps involved in the method for manufacturing this IC package.
Referring first to
FIG. 1A
, the IC package is to be constructed on a leadframe
10
which is formed with two major parts: a die pad
16
in the center and a number of package pins
22
on the periphery of the die pad
16
. In the packaging process, the first step is to perform a die-attach process so as to mount a chip
20
(which is a die cut apart from a fabricated wafer) on the front side of the die pad
16
.
Referring next to
FIG. 1B
, in the subsequent step, a wire-bonding process is performed so as to connect the bonding pads (not shown) on the chip
20
respectively via a plurality of wires
24
to the corresponding ones of the package pins
22
.
Referring further to
FIG. 1C
, in the subsequent step, a molding process is performed so as to form a molded compound
26
which hermetically encloses the chip
20
, the die pad
16
, and the wires
24
therein, with only the outer end of the package pins
22
being exposed to the outside.
In the case of the foregoing IC package being used to enclose an ordinary chip other than EPROM or EEPROM, the molded compound
26
can be formed from a lowcost material, such as plastics. However, in the case of the foregoing IC package being used to enclose an EPROM chip or an EEPROM chip therein, the molded compound
26
should be formed with a transparent window that can allow ultraviolet light to pass therethrough during a reprogramming process to erase old data from the chip and program new data into the same. To provide the transparent window, a special (and relatively costly) material, such as ceramics, is used to form the molded compound
26
. The high manufacturing cost of these IC packages make them considerably more expensive on the market.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide an IC package architecture and a method of manufacturing the same, which are useful for forming a transparent window in such IC products as EPROM and EEPROM with a considerably reduced manufacturing cost.
It is another an objective of the present invention to provide an IC package architecture and a method of manufacturing the same, which allow the manufacturer to form a variable dispensed compound to enclose the chip from a suitably selected material that can variably selected to be either a transparent material so as to allow the enclosed chip to be transparent to the outside, or a colored material for some prespecified identification purpose of the IC package.
It is still another objective of the present invention to provide an IC package architecture and a method of manufacturing the same, which have the above-mentioned benefits while nonetheless can be utilized on current types of IC packages and can be realized by using existing equipment and processes in a cost-effective manner without having to invest on new additional ones.
In accordance with the foregoing and other objectives of the present invention, a new IC package architecture and a method of manufacturing the same are provided.
The method of the invention includes the following steps:
(1) preparing a leadframe which includes a die pad and a number of package pins;
(2) performing a molding process with a molding material so as to form a molded compound which covers the entire packaging area on a first side of the leadframe, but only covers a peripheral part of the packaging area on a second side of the leadframe with a window to expose the bonding area on the second side of the leadframe;
(3) performing a die-attach process so as to mount a chip on the die pad on the second side of the leadframe;
(4) performing a wire-bonding process so as to electrically connect the chip to corresponding ones of the package pins; and
(5) performing a dispensing process with a dispensing material so as to fill the dispensing material into the window to thereby form a dispensed compound in the window to enclose the chip therein.
In another aspect, the IC package architecture of the invention includes the following constituent elements:
(a) a leadframe which includes a die pad and a number of package pins;
(b) a molded compound which covers the entire packaging area on a first side of said leadframe, but only covers a peripheral part of the packaging area on a second side of said leadframe with a window to expose the bonding area on the second side of said leadframe;
(c) a chip mounted on said die pad on the second side of said leadframe;
(d) a plurality of wires which electrically connect said chip to corresponding ones of said package pins; and
(e) a dispensed compound formed in said window on the second side of said leadframe to enclose said chip therein.


REFERENCES:
patent: 5200367 (1993-04-01), Ko
patent: 5893723 (1999-04-01), Yamanaka
patent: 5897338 (1999-04-01), Kaldenberg
patent: 6114189 (2000-09-01), Chia et al.
Tummala, Rao et al., Microelectroni Packaging Handbook, Semiconductor Packaging, Part II, 2nd edition, Chapman & Hall, pp. 394-410 and 420, 1997.

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