Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
2002-09-10
2004-05-11
Cuneo, Kamand (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S786000, C257S690000, C174S260000
Reexamination Certificate
active
06734555
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority on British Patent Application GB 01 21891.6 filed Sep. 11, 2001.
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit package and circuit board arrangement. The invention is applicable to, but not limited to, a contact layout arrangement for integrated circuit packaging.
2. Background of the Invention
Most, if not all, current electrical and electronic equipment uses printed circuit board (PCB) technology to operably couple electronic components together. A typical printed circuit board includes a large number of metalised tracks to facilitate the operable coupling of components.
Such components typically have a plurality of contact points, such as input/output ports, power supply points, ground points, clock signal input/output ports, etc., to interface to other components. In recent times, the complexity of such electronic components and circuits has increased dramatically, to the point now where many electronic components and functions are performed in single or multiple integrated circuit packages.
An integrated circuit (IC) is a complete circuit that is manufactured as a single package. The IC may consist of several separate component parts attached by a ceramic substrate and interconnected by wire bonds or a suitable metalisation pattern. The complexity of circuits being produced on a single chip has been increasing rapidly, where very large scale integration (VLSI) and extra large-scale integration (ELSI) having hundreds of thousands of logic gates on a single chip are becoming commonplace.
Consequently, printed circuit boards have become more complex to design, to facilitate the increase in the number of tracks to link to the various component parts of the IC. As such, in the main, printed circuit boards have evolved to multi-layer arrangements, where each layer contains many tracks. The individual layers are operably connected at strategically designed points using vias, which are metallic connections that link two or more layers in a multi-layer substrate.
In the field of this invention it is known that integrated circuit (IC) packaging has evolved to the situation where each IC package requires a large number of different types of contacts, for example ground contacts, power supply contacts, oscillator/clock contacts, data and other high speed contacts etc.
The inventor of the present invention has identified problems encountered when attempting to route tracks to/from the contacts of IC packaging. These problems are often caused by the particular layout of the contacts of the IC package.
A first problem encountered relates to the power supply contacts of the IC package. As known in the art, power supply contacts require large de-coupling capacitors connected thereto. If a long track is provided between the capacitor and its corresponding power supply contact, the track acts as a resistor. The combination of the capacitance with the induced resistance effectively creates a filtering effect on the power supply signal input to the power supply contact on the IC package. The longer a track to the contact point, the greater is the resistance induced by the track. In this manner, by having a resistance between the capacitor and the power supply contact, the ability for current to flow between the resistor and the power supply contact is reduced. Hence, it is important to provide the shortest amount of track between the capacitor and the power supply contact.
Furthermore, because of the potentially high amount of current that can flow through power supply contacts and tracks, the tracks need to be relatively wide. Therefore, it is also preferable to keep the tracks as short as possible in order to reduce costs and reduce the amount of area on the PCB taken up by such power supply tracks.
A second problem encountered relates to ground connections of IC packages. The problem recognized by the inventor of the present invention relates to the connecting of ground points, contacts and/or layers of an IC package using the aforementioned vias (sometimes termed through-holes), which pass through several layers of a PCB. For electronic devices such as mobile phones, the ground layer is often extended to substantially the entire length and width of the PCB, and designed to act as a shield between radio frequency (RF) circuitry and baseband circuitry. Because of this, baseband circuitry is often arranged to be on the opposite side of the ground-plane (or layer) to the RF circuits/components. Thus, such vias often provide obstructions when trying to route tracks around the PCB.
A third problem encountered arises from the need to connect timing or frequency contacts to oscillator or clock generation circuits, which are used by the IC to provide clock signals etc. These contacts are required to be connected to oscillators, such as quartz, and decoupling capacitors. If tracks used to connect to such components are again too long, parasitic capacitance and induced resistance become significant enough to affect the oscillating signal frequency, and thereby the resulting clock signal(s).
Thus, in order for clock signals to be as accurate as possible, the required components are preferably located as close to the integrated circuit package contacts as possible. Furthermore, clock signals on devices such as mobile phones are prone to interference caused by RF signals. Although the ground layer is often provided between baseband circuitry and RF circuitry, vias and other inter-layer connections can cause apertures in the ground layer, which facilitate the propagation of RF interference.
A need therefore exists for an improved integrated circuit and printed circuit board arrangement, and, in particular, an improved contact layout configuration for an integrated circuit, wherein the abovementioned disadvantages may be alleviated.
SUMMARY OF INVENTION
In accordance with the invention, an arrangement of a plurality of contact points is provided in an integrated circuit package device or a printed circuit board. The plurality of contact points includes an inner portion of the contact points and an outer portion of the contact points, and at least one of the following:
(i) a majority of power supply contacts is configured substantially in an extremity of the outer portion;
(ii) a majority of timing or frequency contacts is configured substantially in the outer portion; and
(iii) a majority of data or high speed signal contacts is configured substantially in an inner side of the outer portion.
In one aspect of the invention, the arrangement is provided in an integrated circuit package device. In another aspect of the invention, the arrangement is provided in a printed circuit board having a plurality of tracks for operably coupling electrical signals to the plurality of contact points.
Preferably, ground contacts are further provided along a bisectional axis through the outer portion to facilitate a ground path from outside an area of either the integrated circuit package device or the PCB to the inner portion. The inner portion can be farmed substantially of ground contact points to effect a ground plane. Also, the inner portion and the outer portion arc preferably two distinct regions separated by a space.
Further aspects of the invention are as claimed in the dependent claims.
In summary, the present invention proposes inter-alia, to arrange the positioning of an IC package's interface ports/contact points to facilitate an easier, more accurate and more reliable printed circuit board layout.
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Cruz Lourdes
Cuneo Kamand
McGarry Bair PC
Sendo International Limited
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