Integrated circuit package and manufacturing method thereof

Details Integrated circuit package and manufacturing method thereof Integrated circuit package and manufacturing method thereof

2008-08-29

2011-11-08

Datskovskiy, Michail V (Department: 2835)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S258000, C174S260000, C174S262000, C361S760000, C361S762000, C361S763000, C361S764000, C257S099000, C257S777000, C257SE21505, C257SE33075, C029S829000, C029S830000, C029S832000, C029S846000, C029S852000, C438S118000, C438S122000, C438S654000

Reexamination Certificate

active

08053681

ABSTRACT:
An IC package includes: a multi-layered PCB having a plurality of insulating layers and a plurality of conductive pattern layers stacked in sequence and a plurality of via-holes formed through the plurality of the insulating layers for an electrical connection between the layers; and an IC chip disposed in a core insulating layer of the plurality of the insulating layers to be embedded in the multi-layered PCB and including a plurality of input/output pads on their surface. The input/output pads disposed at an outermost area of the IC chip are coupled to outer terminals by connection members without passing through said via-hole, the remaining input/output pads except for the input/output pads disposed at the outermost area of the IC chip are coupled to the outer terminals through the via-hole.

REFERENCES:
patent: 6909054 (2005-06-01), Sakamoto et al.
patent: 6969916 (2005-11-01), Shizuno
patent: 7282394 (2007-10-01), Cho et al.
patent: 7285728 (2007-10-01), Sunohara et al.
patent: 7414309 (2008-08-01), Oi et al.
patent: 7435910 (2008-10-01), Sakamoto et al.
patent: 7842887 (2010-11-01), Sakamoto et al.
patent: 7885342 (2011-02-01), Brainos et al.
patent: 7894203 (2011-02-01), Kariya et al.
patent: 2009/0316373 (2009-12-01), Kim et al.

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