Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Reexamination Certificate
2005-09-06
2005-09-06
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Output switching noise reduction
C326S038000, C326S039000, C326S083000, C326S086000, C326S115000, C326S127000
Reexamination Certificate
active
06940302
ABSTRACT:
Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.
REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4486739 (1984-12-01), Franaszek et al.
patent: 4527079 (1985-07-01), Thompson
patent: 4658156 (1987-04-01), Hashimoto
patent: 4853560 (1989-08-01), Iwamura et al.
patent: 5059835 (1991-10-01), Lauffer et al.
patent: 5067007 (1991-11-01), Otsuka et al.
patent: 5144167 (1992-09-01), McClintock
patent: RE34808 (1994-12-01), Hsieh
patent: 5521530 (1996-05-01), Yao et al.
patent: 5557219 (1996-09-01), Norwood et al.
patent: 5589783 (1996-12-01), McClure
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5742178 (1998-04-01), Jenkins, IV et al.
patent: 5801548 (1998-09-01), Lee et al.
patent: 5936423 (1999-08-01), Sakuma et al.
patent: 5939904 (1999-08-01), Fetterman et al.
patent: 5958026 (1999-09-01), Goetting et al.
patent: 5970255 (1999-10-01), Tran et al.
patent: 6175952 (2001-01-01), Patel et al.
patent: 6215326 (2001-04-01), Jefferson et al.
patent: 6236231 (2001-05-01), Nguyen et al.
patent: 6252419 (2001-06-01), Sung et al.
patent: 6271679 (2001-08-01), McClintock et al.
patent: 6366128 (2002-04-01), Ghia et al.
patent: 6400598 (2002-06-01), Nguyen et al.
patent: 6407576 (2002-06-01), Ngai et al.
patent: 6433579 (2002-08-01), Wang et al.
patent: 6686772 (2004-02-01), Li et al.
patent: 6812733 (2004-11-01), Plasterer et al.
patent: 2002/0190751 (2002-12-01), Lee et al.
patent: 2004/0113656 (2004-06-01), Sato
patent: 0 575 124 (1993-12-01), None
“A-3.3-V Programmable Logic Device that Addresses Low Power Supply and Interface Trends,” IEEE 1997 Custom Integrated Circuits Conference, May 1997, pp. 539-542.
“APEX20KC Programmable Logic Device Data Sheet”, Apr. 2002 ver. 2.1, pp. 1-6 & 36-48.
“APEX II Programmable Logic Device Family Data Sheet”, Apr. 2001, ver. 1.0, pp. 24-38.
“Block Diagram for NSM LVDS Output Buffer”, “Circuit Trace from National Semiconductor Device”, National Semiconductor Corporation, no date.
“Lucent Introduces 10Gb/s Ethernet FPGAs”, Programmable Logic News and Views, Electronic Trend Publications, Inc., vol. IX, No. 11, Nov. 2000, pp. 7-8.
“LVDS Owner's Manual; Design Guide”, National Semiconductor Corporation, Spring 1997, Chapter 1, pp. 1-7, no month.
Mecury Programmable Logic Device Family Data Sheet, Mar. 2002, ver. 2.0, pp. 1-2,& 47-60.
“ORCA ORT82G5 0.622/1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface FPSC”, Product Brief, Feb. 2001, Lucent Technologies Inc., pp. 1-8.
“Protocol Independent Gigabit Backplane Transceiver Using Lucent ORT4622/ORT8850 FPSCs”, Application Note, Jun. 2000, Lucent Technologies Inc., pp. 1-10.
“Using HSDI In Source-Synchronous Mode in Mercury Devices, Application Note 159”, Altera Corporation, Sep. 2001, ver. 1.0., pp. 1-60.
“Using Phase Locked Loop (PLLs) in DL6035 Devices, Application Note”, Dyna Chip Corporation, Sunnyvale, CA, 1998, pp. i and 1-6, no date.
“Using the Virtex Delay-Locked Loop, Application Note, XAPP132, Oct. 21, 1998 (Version 1.31)”, Xilinx Corporation, Oct. 21, 1998, pp. 1-14.
“Virtex™-E 1.8V Field Programmable Gate Arrays Preliminary Product Specification”, Xilinx, DS022-2 (vs.3), Nov. 9, 2001, pp. 1-3 & 30-52.
“Virtex-II 1.5V Field-Programmable Gate Arrays Advance Product Specification”, Xilinx, DS031-2(v2.0), Jul. 16, 2002.
“Virtex 2.5V Field Programmable Gate Arrays, Advanced Product Specification, Oct. 20, 1998 (Version 1.0)”, Xilinx Corporation, Oct. 20, 1998, pp. 1-24.
DY6000-Family, FAST Field Programmable Gate Array, DY6000 Family Datasheet, Dyna Chip Corporation, Sunnyvale, CA, Dec. 1998, pp. 1-66.
Optimized Reconfigurable Cell Array (ORCA), OR3Cxxx/OR3Txxx Series Field-Programmable Gate Arrays, Preliminary Product Brief, Lucent Technolgies Inc., Microelectronics Group, Allentown, PA, Nov. 1997, pp. 1-7 and unnumbered back cover.
ORCA Series 3 Field-Programmable Gate Arrays, Preliminary Data Sheet, Rev. 01, Lucent Technologies Inc., Microelectronics Group, Allentown, PA, Aug. 1998, pp. 1-80.
Rocket I/O Transceiver User Guide, UG024 (vl.2) Feb. 25, 2002, Xilinx, Inc., pp. 1-106.
Virtex-II Pro Platform FPGA Handbook, UG012 (vl.0) Jan. 31, 2002, Xilinx, Inc., pp. 1-6, 27-32, 121-126, and 162-180.
Patel Rakesh H.
Shumarayev Sergey Y.
White Thomas H.
Wong Wilson
Altera Corporation
Fish & Neave IP Group of Ropes & Gray LLP
Jackson Robert R.
Lin Hong S.
Tan Vibol
LandOfFree
Integrated circuit output driver circuitry with programmable... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit output driver circuitry with programmable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit output driver circuitry with programmable... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3387646