Integrated circuit module has common function known good...

Details Integrated circuit module has common function known good... Integrated circuit module has common function known good...

1999-02-08

2002-03-12

Lee, Thomas (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

C257S738000, C257S666000, C439S441000

Reexamination Certificate

active

06356958

ABSTRACT:

FIELD OF THE INVENTION
This invention is related to integrated circuits. More particularly, this invention relates to multiple function integrated circuit chips such as Dynamic Random Access Memories (DRAM) having function selection through wiring connections on a second level substrate onto which an integrated circuit chip is mounted.
BACKGROUND OF THE RELATED ART
The structure of a DRAM is well known in the art. Usually a DRAM chip is configured to be organized as a ×1 (by 1), ×4 (by 4), ×8 (by 8), or ×16 (by 16) package by selective destruction of fuses internal to the DRAM chip and by selectively connecting the data input/output pads to pins on a package. The unused pins are not connected to the input/output pads of the undesired or unused data transfer pads. Refer now to
FIG. 1
for a schematic drawing of the structure of a DRAM integrated circuit showing the input/output selection function. A DRAM array
100
has multiple banks of arrays of DRAM cells. Address signals are applied to the address I/O's
105
and decoded within column address and row address decoders to select DRAM cells within the DRAM array
100
.
Control and timing signals
120
are applied to the control logic and timing generator
115
to provide the necessary control and timing functions for the DRAM array
100
.
Upon applying an address to the DRAM array
100
, digital data is transferred to or from the DRAM array
100
by the internal data bus
110
. The internal data bus
110
is connected between the sense amplifier and I/O bus on each memory bank. The internal data bus
110
may conceptually have a connection for each column of one memory bank, but usually is the maximum data bit width configuration of the DRAM integrated circuit.
The internal data bus
110
is connected to the input/output selector
125
. The input/output selector
115
determines the interconnections between the input/output buffers
130
and the internal data bus
110
. The selection pins
140
of the input/output selector
125
are connected to the selection networks formed of the resistors
145
a
,
145
b
, and
145
c
and the fuses
150
a
,
150
b
, and
150
c
. A logical one state is applied to the selection pins
140
, if a fuse
150
a
,
150
b
, and
150
c
is opened. A logical zero state is applied to the selection pins
140
, if a fuse
150
a
,
150
b
, and
150
c
remains intact. The logical states applied to the selection pins
140
determine which connections on the internal data bus
110
are connected to which of the input/output buffers
130
. While, as shown, the selector circuits will draw unacceptable amounts of standby current, it is presented here for illustration. Other techniques known in the art are used to form the selection networks.
The semiconductor wafer is placed on a test system and each integrated circuit chip is tested
215
for functionality. The functioning chips are denoted as functional die. The semiconductor wafer is then diced
220
and the functional die are separated for further assembly
225
in a first level or module package. The selection or omission of connections between the functional integrated circuit die and the first level package is a custom design particular to each combination of desired functions.
Those input/output pads
135
not used for a configuration are not connected to the module connections during the next level assembly. The fused configuration selection forces the maintenance of inventory of the DRAM die for each desired configuration increasing the difficulty in planning of production of DRAM wafers.
While the structure of the prior art as shown in
FIG. 1
is described for a DRAM, other integrated circuit functions such as computational processors (microprocessors, microcontrollers, digital signal processors, etc.), programmable memory, and programmable logic arrays employ metal masking or fuse destruction at the wafer level, and making or omitting connections during attachment of the functional integrated circuit die to a next level package assembly. This complicates the semiconductor processing in that extra masking steps are required for mask programming of desired functions of the functional integrated circuit die. Each function desired requires a unique mask for the selection process, further complicating the semiconductor process. Additionally, fuse destruction adds an extra step in the processing of the functional integrated circuit die.
FIG. 2
shows a process for forming integrated circuit modules. The process begins with the formation
200
of the integrated circuit chip on a semiconductor wafer. The semiconductor process
210
forms the collection of transistors that are the electronic circuits on the semiconductor wafer. The electronic circuits are interconnected by metalization and are also connected to input/output pads by the metalization placed on the surface of the semiconductor wafer. During the metalization, optional functions may be personalized to select optional functions. In the case of the DRAM of
FIG. 1
, the fuses
150
a
,
150
b
, and
150
c
are either opened or held intact during this process to select the desired input/output organization options. An alternative to selecting the desired input/output organization options of the DRAM of
FIG. 1
is exposing the metalization on the surface of the semiconductor substrate that forms the fuses
150
a
,
150
b
, and
150
c
to intense laser light to destroy the appropriate fuses
150
a
,
150
b
, and
150
c.
The steps of formation of the integrated circuit chip is common for all the desired selectable functions until the metalization to select the desired functions. The integrated circuit chips then becomes a custom design. Equally, the integrated circuit chip has a common design until the destruction of fuses to create the custom personalization that selects each desired function of the integrated circuit chip.
The semiconductor wafer is placed on a test system and each integrated circuit chip is tested
220
or functionality. The functioning chips are denoted as functional die. The semiconductor wafer is then diced
220
and the functional die are separated for further assembly
225
in a first level or module package. The selection or omission of connections between the functional integrated circuit die and the first level package is a custom design particular to each combination of desired functions.
The input/output pads of the desired functions of the functional die are connected by a method such as wire bonding or tape automated bonding to the pins of the first level package. The input/output pads of the undesired function are omitted during the wire bonding or tape automated bonding. The package is tested
230
and inventoried
235
for further assembly.
The assembly
205
of the second level package begins by forming
240
the substrate of the second level assembly. Multiple layers substrate are formed having interconnection metalization that connects the packaged and tested die to external circuitry that is present either on the second level package or elsewhere within the electronic system. The multiple layers are assembled to form the substrate of the second level assembly.
A solder mask is placed
245
on the second level assembly and a solder paste is placed
250
at all connection points of the packaged and tested die. The packaged and tested die is attached
255
to the second level assembly. In a surface mounted packaging system, the solder paste is melted and the pins of the packaged and tested die fused to the metalization of the second level assembly. The remaining processing of the second level assembly is completed
260
.
For integrated circuit modules having multiple functions, the metalization of the second level assembly must be customized. Again, this increases the number of assembly types required to be inventoried.
U.S. Pat. No. 5,360,992 (Lowery et al.) discloses a semiconductor package which allows pinouts and bond options to be customized after encasement of a semiconductor die. The semiconductor package has two assemblies in

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