Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2008-02-29
2010-02-09
Luu, Pho M. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S185020, C365S191000, C365S226000
Reexamination Certificate
active
07660175
ABSTRACT:
An embodiment of an integrated circuit comprises a plurality of cells. Each cell comprises a first supply node, a second supply node, a series connection with a first transistor, a second transistor and an electrical element. The series connection is coupled between the first and the second supply node. The electrical element includes a first and a second node. A third transistor is coupled between the first node of the electrical element and a first output node of the cell and a fourth transistor is coupled between the second node of the electrical element and the second output node of the cell. A control terminal of the first, the third and the fourth transistor is coupled to a first control node of the cell and a control terminal of the second transistor is coupled to a second control node of the cell.
REFERENCES:
patent: 5361232 (1994-11-01), Petschauer et al.
patent: 5453954 (1995-09-01), Nakamura
patent: 5675539 (1997-10-01), Mirabel et al.
patent: 6865113 (2005-03-01), Voicu et al.
Duschinger Bernhard
Hermann Josef
Holmer Rainer
Kohlert Dieter
Mackh Gunther
Infineon - Technologies AG
Luu Pho M.
Slater & Matsil L.L.P.
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