Integrated circuit method

Details Integrated circuit method Integrated circuit method

1983-08-12

1984-12-04

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29571, 29576W, 29580, 148187, 156648, 156653, 156656, 156662, 427 88, 430313, H01L 21306, H01L 744, C23F 102, B05D 512

Patent

active

044862660

ABSTRACT:
A CMOS integrated circuit made up of complementary insulated gate field effect transistors incorporates isolation trenches formed by a combination of thermal growth of silicon dioxide and chemical vapor deposition of polycrystalline silicon to prevent air gaps. Matching of the thermal coefficient of expansion of the trench with that of the substrate minimizes pn junction leakage currents as well as positive feedback latch-up operation. To reduce the ohmic contact resistance and interconnect resistance of the transistor elements, refractory metal silicide areas of low sheet resistance are contacted with the source, drain and gate elements. The process of manufacture also employs vertical walls of silicon nitride to prevent the formation of "birds' beak" portions of increased thickness in the silicon dioxide layer of each transistor, which could degrade the high frequency performance of the device.

REFERENCES:
patent: 4140558 (1979-02-01), Murphy et al.
patent: 4443933 (1984-04-01), de Brebisson

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