Static information storage and retrieval – Read/write circuit
Patent
1992-08-18
1993-11-23
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
365203, 36523006, G11C 1140
Patent
active
052650502
ABSTRACT:
A DRAM or VRAM integrated circuit memory of the divided bit line design includes a bit line pair extending from a column decoder to a SAM. An N-sense amplifier divides the bit line pair into two pairs of bit line halves. The N-sense amplifier is connected to each of the bit line halves through an isolation transistor. A P-sense amplifier is connected across each pair of the bit line halves. The timing signals enabling and disabling the isolation transistors and the P-sense amplifiers are designed so that during an access of the bit line halves nearest the data port, the isolation of the N-sense amplifier and the associated P-sense amplifier from the bit line halves distal from the data port is extended through the P-sense amplifier cycle and into the precharge cycle, thereby charging only the bit line halves nearest the port and saving power. In another embodiment, a single P-sense amplifier is connected across the bit line pair adjacent the N-sense amplifier between the isolation transistors, with the same isolation timing and power saving results.
REFERENCES:
patent: 4636987 (1987-01-01), Norwood et al.
patent: 4748349 (1988-05-01), McAlexander et al.
patent: 5103113 (1992-04-01), Inui et al.
Fears Terrell W.
Micro)n Technology, Inc.
LandOfFree
Integrated circuit memory with isolation of column line portions does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit memory with isolation of column line portions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit memory with isolation of column line portions will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1854948