Integrated circuit memory with dual P-sense amplifiers associate

Details Integrated circuit memory with dual P-sense amplifiers associate Integrated circuit memory with dual P-sense amplifiers associate

1992-08-18

1994-06-21

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Differential sensing

365206, 365207, 36518901, G11C 1140

Patent

active

053233506

ABSTRACT:
A DRAM or VRAM integrated circuit memory of the divided bit line design includes a bit line pair extending from a column decoder to a SAM. An N-sense amplifier divides the bit line pair into two pairs of bit halves. The N-sense amplifier is connected to each of the bit line halves through an isolation transistor. A P-sense amplifier is connected across each pair of the bit line halves. Since a P-sense amplifier is associated with each pair of bit line halves, the P-sense amplifier never has to pull through isolation transistors, and thus the isolation transistors can be high threshold transistors, eliminating the natural threshold mask step in fabrication. The two P-sense amplifiers separate the bit line voltages faster, thereby decreasing crossing current and saving power, and pull the bit lines to full high voltage levels.

REFERENCES:
patent: 4636987 (1987-01-01), Norwood et al.
patent: 4748349 (1988-05-01), McAlexander, III et al.
patent: 5053997 (1991-10-01), Miyamoto et al.

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