Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1995-04-24
1996-03-26
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Bad bit
365177, 3652256, G11C 700
Patent
active
055026761
ABSTRACT:
An integrated circuit memory (30) having redundancy shares read, global data lines shared between a regular memory array (35) and a plurality of redundant columns (41). Redundant data and regular data are multiplexed onto the read global data lines by emitter summing bipolar transistors of regular sense amplifiers (46) with a redundant multiplexer (83). When a redundant column is used to replace a defective regular column, a match circuit (88) generates a match signal for selecting a redundant multiplexer circuit (84, 85, or 86) and for deselecting a corresponding regular sense amplifier (46). The match circuit (88) includes emitter summing circuits (230, 240) to rapidly generate the match signal.
REFERENCES:
patent: 4837747 (1989-06-01), Dosaka
patent: 4881200 (1989-11-01), Urai
patent: 5163023 (1992-11-01), Ferris
patent: 5293348 (1994-03-01), Abe
Ghassemi Hamed
Pelley III Perry H.
Hill Daniel D.
Mai Son
Motorola Inc.
Nelms David C.
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