Integrated circuit memory with a bus transceiver

Details Integrated circuit memory with a bus transceiver Integrated circuit memory with a bus transceiver

1998-09-24

2001-01-02

Thai, Tuan V. (Department: 2751)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S100000, C711S104000, C711S131000, C711S154000

Utility Patent

active

06170041

ABSTRACT:

The present invention relates generally to integrated circuit memory devices, and more particularly to two port integrated circuit memory devices that broadcast signals received at one port to the second port.
BACKGROUND OF THE INVENTION
A conventional computer system, as illustrated in
FIG. 1
, includes at least one processor, one or more random access memory (RAM) arrays, read only memory (ROM), a non-volatile memory such as a flash memory, and a custom logic device (ASIC). These components are coupled together by a system bus. As the operating frequencies of processors has increased, the high capacitive loading of system buses have made them a bottleneck in system performance. For example, in a typical system the difference between a 75 pF load on a bus and a 15 pF load on a bus is about 1.25 ns. If the cycle time of the processor is 10 ns, then this represents over 10% of the cycle time. The capacitive loading thereby reduces the access time available to access devices in a clock cycle and therefore may require additional wait-states to be used to access external memory. Large capacitive loading may also require using faster, more expensive devices to meet desired system performance requirements. Large capacitive loading and faster external devices also increase the power consumption of the system.
One conventional approach to reducing bus capacitance and increasing system clock rates is to split the system bus into two or more buffered component buses. The capacitance of each individual bus is thereby reduced allowing the use of higher bus clock rates. However, each buffer stage in the bus introduces delays, which typically requires wait states to be added for accessing devices. A further source of delay in conventional systems is that each time a signal must be communicated from one integrated circuit chip to another, typically a wait state must be added.
An object of the present invention is to overcome these and other problems of the prior art so as to provide high speed access to a memory array while supporting reduced speed access to other slower devices.
SUMMARY OF THE INVENTION
In summary, the present invention is a two port high speed integrated circuit memory device that includes a bus transceiver, a memory array and a decoder. The present invention provides a processor high speed access to an internal memory array via very low capacitive load address and data buses. The present invention also buffers a secondary bus to provide access to slower-speed local devices. The bus transceiver transfers address, data and control signals between the primary and secondary port and also couples signals to the internal memory array. In one embodiment signals are coupled from the primary or secondary port to the internal memory array within the current clock cycle so as to provide no wait state performance up to 133 MHz. The bus transceiver includes an input data bus, an output data bus, and an address and control bus. Each of these separate buses include a buffer at the primary and secondary port to minimize capacitive loading. The roles of the primary and secondary bus can be reversed in most modes of operation.
The decoder in the two port memory device decodes memory chip select signals and control signals that define the operational mode of the device. In one system configuration, there are three address spaces: program space, data space, and I/O space. Each of these address spaces further includes an upper and a lower section. In one embodiment, two of these address space sections can be mapped to the internal memory array and the other four are mapped to external memory. Access to these address spaces is controlled by the chip select signals decoded by the decoder. When the lower halves of two address spaces or the upper halves of two address spaces are mapped into the internal memory array, the most significant address line is inverted for addresses to one of the address spaces to distinguish addresses for the two memory spaces. Further, to save power the present invention provides an operational mode in which primary bus signals are not reflected to the secondary bus unless the internal memory array is not selected by the chip selects.
In an enhanced mode the two port memory device includes a ready signal generator feature. Also, in the enhanced mode chip select lines are converted into additional address input lines. An output enable control pin is converted into a clock input, and a write enable pin is converted into a ready signal output. The delay between a clock start strobe signal and the ready signal is programmable by writing to internal registers. Generating the ready signal in the two port memory device avoids the need to insert any wait states for transferring signals to an external logic chip to provide ready signals.


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