Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2007-08-07
2007-08-07
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S206000, C365S230030
Reexamination Certificate
active
10954941
ABSTRACT:
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.
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Bellows Chad A.
Ching Michael
Kim Jun
Knorpp Kurt T.
Richardson Wayne S.
Hoang Huan
Morgan & Lewis & Bockius, LLP
Rambus Inc.
Tran Anthan
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