Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
1999-09-20
2001-01-30
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S208000, C365S205000, C365S190000, C365S195000, C365S196000, C365S189080, C365S230060, C365S233100
Reexamination Certificate
active
06181624
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated memory.
U.S. Pat. No. 4,807,193 describes a DRAM having memory cells of the one-transistor/one-capacitor type. Signals read from one of the memory cells onto a bit line are amplified by a sense amplifier. In this case, the memory cell is selected via a word line connected to a control terminal of the memory cell transistor. To ensure that the sense amplifier amplifies the information items that have been read out in good time, it has an activation input, to which an activation signal is fed which is dependent on the potential on the word line. This is intended to ensure that the sense amplifier only becomes active if the potential on the word line has reached a specific level, so that it can be assumed that the memory cell has already been selected via the word line. U.S. Pat. No. 4,807,193 relates to a memory with only one word line.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which has a multiplicity of word lines and bit lines, in the case of which memory activation of at least one evaluation unit for evaluating information items read from the memory cells onto the bit lines is effected in a time-optimized manner at least for a plurality of the word lines.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, including:
bit lines;
word lines each having a remote end and intersecting the bit lines;
a cell array having memory cells for storing information items, the memory cells are disposed at crossover points of the bit lines and the word lines;
a word line decoder connected to and addressing the word lines;
at least one evaluation unit has an activation input and is connected to the bit lines, the at least one evaluation unit evaluating the information items read from the memory cells and deposited onto the bit lines; and
a logic unit for performing an OR function having inputs connected to the remote end of each of the word lines being remote from the word line decoder and having an output connected to the activation input of the at least one evaluation unit.
The integrated memory according to the invention has memory cells for storing information items, which are disposed in a cell array at crossover points of bit lines and word lines. Furthermore, it has a word line decoder, by which the word lines can be addressed, and at least one evaluation unit for evaluating information items read from the memory cells onto the bit lines and the evaluation unit has an activation input. Moreover, it has a logic unit for performing an OR function having inputs connected to that end of each of the word lines which is remote from the word line decoder, and has an output connected to the activation input of the evaluation unit.
The integrated memory may be any desired memory having bit lines and word lines as well as at least one corresponding evaluation unit. Therefore, the invention is suitable both for writeable memories such as DRAMs, SRAMs, flash memories and EEPROMs and for read-only memories (ROMs).
Since the logic unit is connected to those ends of the word lines which are remote from the word line decoder, selection of a specific one of the word lines by the decoder and an associated change in the potential of the word line affect the inputs of the logic unit only when the entire word line has undergone charge reversal. The propagation of the new signal level on the word line takes place proceeding from the decoder in the direction of that end of the word line which is remote from the decoder. Connecting the logic unit to the ends of the word lines therefore has the advantage that even that memory cell of the memory cells connected to the word line which is the furthest away from the decoder has been reliably selected if the level change of the word line currently addressed by the decoder has an effect at the input of the logic unit. Consequently, the logic unit influences the activation input of the evaluation unit only when a level change becomes apparent at that end of the respective word line which is remote from the word line decoder. The invention furthermore has the advantage that the activation of the evaluation unit is carried out in a time-optimized manner for all of the word lines connected to the logic unit. This is ensured by the OR function of the logic unit. For each individual word line of the word lines connected to the logic unit, the evaluation unit is activated only when a level change has occurred at the respective input of the logic unit.
According to a development of the invention, the integrated memory is a dynamic memory (DRAM) of the one-transistor/one-capacitor type, whose memory cells each have a storage capacitor, whose first electrode is connected to a fixed first potential and whose second electrode is connected to one of the bit lines via a selection transistor. Furthermore, its cell array has end cells at its edge, which end cells, in contrast to the memory cells, do not serve for storing information items but rather for optimizing a process for fabricating the memory cells and are configured essentially like the memory cells, in each case with a capacitor as well as a selection transistor. In this case, at least some of those end cells which are disposed on a side of the cell array which is remote from the word line decoder are component parts of the logic unit and control inputs of the selection transistors of these end cells are the inputs of the logic unit. In this case, that terminal of the selection transistors of the end cells which is remote from the capacitor is connected to a line which is connected to the output of the logic unit, and that terminal of the capacitor of the end cells which faces the selection transistor is connected to a fixed second potential.
The end cells, which serve for process optimization during the fabrication of the memory cells, promote, during the fabrication, the production of the different layers from which the integrated memory is fabricated. By way of example, the storage capacitors of the memory cells may be trench capacitors. In order to fabricate them, trenches are produced in a substrate and the capacitors with their electrodes are formed in the trenches. Since these trenches have to be filled with different materials for the purpose of fabricating the electrodes and/or for the purpose of carrying out subsequent fabrication steps, irregularities such as e.g. elevations are produced at the edge of a memory cell array to be fabricated with trench capacitors in the course of the application of the layers. This is due to the fact that the trenches of the memory cell array take up a larger amount of the layer material than the regions next to the memory cell array which do not have trenches. Therefore, end cells, which do not usually have an electrical function, are produced in addition to the memory cells at the edge of the cell array. Since the end cells are configured essentially like the memory cells, the capacitors of the end cells are likewise trench capacitors, if the storage capacitors of the memory cells are trench capacitors. As a result of the end cells at the edge of the memory cell array, it is then ensured that the layers produced in the region of the memory cells which are situated within the memory cell array are very uniform. Any influencing of the layers produced by the transition between trench structures present in the cell array and regions without trenches outside the memory cell array then occurs only in the edge region of the cell array, where the end cells are disposed. The memory cells remain uninfluenced by this.
The described development of the invention has the advantage that the end cells that do not usually serve an electrical function are used for realizing the logic unit. This obviates corresponding additionally necessary components that would have to be provided if t
Le Thoai-Thai
Lindolf J{umlaut over (u)}rgen
Schneider Helmut
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
Tran Andrew Q.
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