Integrated circuit memory devices that utilize data masking...

Details Integrated circuit memory devices that utilize data masking... Integrated circuit memory devices that utilize data masking...

2000-09-22

2001-08-07

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230080

Reexamination Certificate

active

06272068

ABSTRACT:

RELATED APPLICATION
This application is related to Korean Application No. 98-28847, filed Jul. 16, 1998, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly to integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Single data rate (SDR) synchronous DRAM integrated circuits have been developed in order to improve the performance of conventional dynamic random access memory (DRAM) integrated circuits. In additional, double data rate (DDR) synchronous DRAM integrated circuits have been developed in order to improve the performance of single data rate synchronous DRAM integrated circuits. Single data rate synchronous DRAM integrated circuit devices process one data value during one period of a clock signal. Double data rate synchronous DRAM integrated circuits process two data values during one period of a clock signal. Therefore, the double data rate synchronous DRAM integrated circuit can have a data processing speed twice as high as that of the single data rate synchronous DRAM integrated circuit.
Because the double data rate synchronous DRAM integrated circuit has a very high data processing speed, the performance of the double data rate synchronous DRAM integrated circuit typically cannot be tested with low speed data equipment. For example, the operating frequency of the double data rate synchronous DRAM integrated circuit presently is about 100 MHz and the operating frequency of conventional test equipment for testing a wafer on which DRAM integrated circuits are arranged presently is only about several MHz (e.g., 5 MHz). Also, since the double data rate synchronous DRAM integrated circuit has a specific pin called a data strobe, the double data rate synchronous DRAM integrated circuit typically can only be tested by enabling the data strobe pin from the outside. Since conventional test equipment typically does not have the capability of enabling the data strobe pin, double data rate synchronous DRAM integrated circuits typically cannot be tested with conventional test equipment. Thus, notwithstanding the advantages of double data rate SDRAM deices, there continues to be a need for improved techniques to test such devices using conventional test equipment.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide integrated circuit memory devices that can be accurately and reliably tested using conventional test equipment.
These and other objects, advantages and features of the present invention can be provided by a double data rate (DDR) synchronous dynamic random access memory device (SDRAM) that comprises a memory cell array and a mask signal generator that generates first and second internal data masking signals (e.g., DM_F, DM_S) during test mode, in response to at least one single data rate mode signal (e.g., CL
1
). A data controller is also provided to pass input write data to the memory cell array when the first and second internal data masking signals are inactive during normal operation and mask at least a portion of the input write data from the memory cell array when one of the first and second internal data masking signals (e.g., DM_S) is active during test mode operation. This ability to mask data facilitates operation of the DDR SDRAM in a specialized single data rate (SDR) mode for testing using conventional test equipment.
Moreover, according to a preferred aspect of the present invention, the mask signal generator is responsive to first and second single data rate mode signals (CL
1
, BL
1
) and comprises a buffer that has a data input that receives an external data strobe signal (DS) and a control input that receives one of the first and second single data rate mode signals (e.g., CL
1
). The mask signal generator also preferably comprises an internal data strobe signal generator that receives as inputs a data strobe clock signal (PCLKDS) and an output of the buffer, and generates an internal data strobe signal (PDS). The mask signal generator may also comprise a NAND gate that receives as inputs an internal clock signal and one of the first and second single data rate mode signals (e.g., CL
1
) and generates the data strobe clock signal (PCLKDS) in response thereto. A mask signal controller is also preferably provided. The mask signal controller generates first and second internal data masking signals (DM_F, DM_S) in response to the internal data strobe signal (PDS) and a data masking signal (DM). The mask signal controller is also responsive to one of the first and second single data rate mode signals (e.g., CL
1
) and the data controller is responsive to the internal data strobe signal (PDS).


REFERENCES:
patent: 5521878 (1996-05-01), Ohtani et al.
patent: 5703828 (1997-12-01), Park et al.

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