Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2000-08-09
2002-06-11
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230060
Reexamination Certificate
active
06404693
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit memory devices and operating methods therefor, and more particularly to controlling selection of memory sub-array blocks during data input/output.
BACKGROUND OF THE INVENTION
Integrated circuit memory devices are widely used in consumer and industrial applications. In general, memory devices include memory cell array blocks comprising a plurality of memory cells, peripheral circuits for controlling the memory cell array blocks and for writing and/or reading data to/from the memory cells. As the capacity of memory devices becomes larger and memory devices become more highly integrated, the area of the memory cell array blocks may become larger. As a result, the area of the integrated circuit may increase.
In particular, in a Dynamic Random Access Memory (DRAM), the memory cell array blocks are generally divided into a plurality of sub-array blocks, and bit line sense amplifiers, column select transistors, bit line equalizing transistors, isolation transistors, and/or input/output lines are arranged in each of the sub-array blocks. These elements are well known to those skilled in the art and need not be described further herein.
In conventional DRAM structures, the number of input/output lines may be determined by the number of bits of data to be simultaneously written and/or read, that is, by the desired bandwidth. Accordingly, in conventional DRAM structures, when increasing the bandwidth, the number of the input/output lines may increase. As a result, the area of the memory cell array blocks may increase, so that the area of the integrated circuit may increase.
SUMMARY OF THE INVENTION
Integrated circuit memory devices according to embodiments of the invention include a memory cell block comprising a plurality of sub-array blocks and a first plurality of input/output line pairs adjacent each of a pair of opposing sides of each of the sub-array blocks. A circuit is configured to select one of the sub-array blocks and to input/output the first plurality of bits of data through the first plurality of input/output line pairs adjacent each of the pair of opposing sides of the selected one of the sub-array blocks. The circuit is further configured to select the second plurality of the sub-array blocks that is greater than one and to input/output the first plurality times the second plurality of bits of data through the first plurality of input/output line pairs adjacent each of a pair of opposing sides of the selected second plurality of the sub-array blocks. The second plurality preferably is an even integer. Accordingly, the number of input/output lines need not increase even when the bandwidth increases.
Other embodiments of integrated circuit memory devices include a memory. cell array block comprising a plurality of sub-array blocks and a number N (where N is an integer) of input/output line pairs arranged on the right and left sides of each of the sub-array blocks. A row decoder circuit selects one of the sub-array blocks in response to a predetermined row address when the bandwidth is 2N bits, and selects two of the sub-array blocks in response to the predetermined row address when the bandwidth is 4N bits. Moreover, 2N bits of data are input/output through 2N input/output line pairs arranged on both sides of one selected sub-array block when the bandwidth is 2N bits, and 4N bits of data are input/output through 4N input/output line pairs arranged on the right and left sides of two selected sub-array blocks when the bandwidth is 4N bits.
In embodiments of the invention, the row decoder circuit includes an input/output select signal generator, a first pre-decoder, a second pre-decoder and a main decoder.
The input/output select signal generator generates an input/output select signal which is activated when the bandwidth is 4N bits. The first row pre-decoder receives the row address, pre-decodes it, and one bit of block select bits of the row address is ignored (“don't care”) when the input/output select signal is activated. The second row pre-decoder receives output signals from the first row pre-decoder, pre-decodes the output signals, and activates two block select signals when one bit of the block select bits is ignored by the first row pre-decoder and activates one block select signal when one bit of the block select bits is not ignored by the first row pre-decoder. The main decoder receives output signals from the second row pre-decoder, selects two of the sub-array blocks, simultaneously activates two predetermined word lines of the two selected sub-array blocks when two block select signals are activated, and selects one of the sub-array blocks and activates one predetermined word line of the one selected sub-array block when one block select signal is activated.
According to method embodiments of the present invention, the first plurality of bits of data are input/output through the first plurality of input/output line pairs adjacent each of a pair of opposing sides of one of the sub-array blocks in response to selection of the one of the sub-array blocks. The first plurality times a second plurality of bits of data are input/output through the first plurality of input/output line pairs adjacent each of a pair of opposing sides of the second plurality of the sub-array blocks in response to selection of the second plurality of the sub-array blocks, wherein the second plurality is greater than one. The second plurality preferably is an even integer.
According to other method embodiments, methods for controlling a memory cell array block in a memory device are provided. The memory cell array block comprises a plurality of sub-array blocks, and a number N (where N is an integer) of input/output line pairs arranged on the right and left sides of each of the sub-array blocks. One of the sub-array blocks is selected in response to a predetermined row address when the bandwidth is 2N bits. Then, 2N bits of data are input/output through input/output line pairs arranged on the right and left sides of one selected sub-array block. Two of the sub-array blocks are selected in response to the row address when the bandwidth is 4N bits. Then, 4N bits are input or output through 4N input/output line pairs arranged on the right and left sides of two selected sub-array blocks.
In other embodiments, the step of selecting one of the sub-array blocks comprises the steps of deactivating an input/output select signal when the bandwidth is 2N bits; responding to one bit of block select bits of the row address when the input/output select signal is deactivated; activating one block select signal when one bit of the block select bits is responded to; and selecting one of the sub-array blocks and activating a predetermined word line of the selected sub-array block when the block select signal is activated.
In other embodiments, the step of selecting two of the sub-array blocks comprises the steps of activating an input/output select signal when the bandwidth is 4N bits; ignoring one bit of block select bits of the row address when the input/output select signal is activated; activating two block select signals when one bit of the block select bits is not ignored; and selecting two of the sub-array blocks and simultaneously activating two predetermined word lines of two selected sub-array blocks when two block select signals are activated.
REFERENCES:
patent: 5701271 (1997-12-01), Lee
patent: 6144220 (2000-11-01), Young
Choi Jong-hyun
Seo Dong-il
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Zarabian A.
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