Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2011-03-08
2011-03-08
Pham, Ly D (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050, C365S191000, C365S194000
Reexamination Certificate
active
07903499
ABSTRACT:
A memory system may include an integrated circuit memory device and a memory controller coupled to the integrated circuit memory device. The integrated circuit memory device may include a memory cell array having a plurality of memory cells, a clock generator configured to generate a clock signal, a plurality of data input/output buffers, and a delay circuit. The plurality of data input/output buffers may be coupled between respective data input/output pads and the memory cell array, and each of the data input/output buffers may be configured to communicate data with the memory cell array responsive to the clock signal with the clock signal being applied to a clock input of each of the input/output buffers. The delay circuit may be coupled between the clock generator and a first one of the data input/output buffers so that the clock signal is delayed by different amounts at clock inputs of the first data input/output buffer and a second one of the data input/output buffers. Moreover, the memory controller may be configured to perform data training. Related methods and memory devices are also discussed.
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Bae Seung-jun
Chung Dae-hyun
Kim Jin-Gook
Kim Sihong
Lee Jae-hyung
Myers Bigel Sibley & Sajovec P.A.
Pham Ly D
Samsung Electronics Co,. Ltd.
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