Integrated circuit memory devices including a dual transistor co

Details Integrated circuit memory devices including a dual transistor co Integrated circuit memory devices including a dual transistor co

1996-05-10

1998-02-03

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36518903, G11C 800

Patent

active

057152098

ABSTRACT:
An integrated circuit memory device includes a plurality of memory units arranged in an array of columns and banks. Each of the memory units includes a memory cell, and a bit line coupled to the memory cell wherein the bit line receives a bit of information from the memory cell. Each of a plurality of global column selection lines extends along a respective column of the memory units through each of the banks. A column decoder generates global column selection signals on the plurality of global column selection lines. Each of a plurality of input/output lines extends along a respective bank of the memory units. In addition, each of a plurality of memory unit selection circuits connects a respective bit line of a respective memory unit to a respective input/output line in response to a global column selection signal on the respective global column selection line and a bank selection column address signal. Accordingly, only one bit line from the plurality of memory units is connected to a respective one of the input/output lines at a time.

REFERENCES:
patent: 5483497 (1996-01-01), Mochizuki et al.
patent: 5499215 (1996-03-01), Hatta
patent: 5535172 (1996-07-01), Reddy et al.
patent: 5566371 (1996-10-01), Ogawa

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