Integrated circuit memory devices having vertically arranged...

Details Integrated circuit memory devices having vertically arranged... Integrated circuit memory devices having vertically arranged...

2011-08-23

2011-08-23

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185020, C365S185170

Reexamination Certificate

active

08004893

ABSTRACT:
Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is also provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. According to these embodiments of the invention, the first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect a gate electrode of the first enhancement-mode transistor to a gate electrode of one of the second plurality of depletion-mode transistors. Similarly, a second string selection plug is configured to electrically connect a gate electrode of the second enhancement-mode transistor to a gate electrode of one of the first plurality of depletion-mode transistors.

REFERENCES:
patent: 5111428 (1992-05-01), Liang et al.
patent: 5994746 (1999-11-01), Reisinger et al.
patent: 6151249 (2000-11-01), Shirota et al.
patent: 7177191 (2007-02-01), Fasoli et al.
patent: 7382018 (2008-06-01), Kim et al.
patent: 7796432 (2010-09-01), Kim et al.
patent: 2007/0165455 (2007-07-01), Park et al.
patent: 11-265997 (1999-09-01), None
patent: 1019990067904 (1999-08-01), None
patent: 1020060089547 (2006-08-01), None
patent: 100673019 (2007-01-01), None
patent: 100707217 (2007-04-01), None
Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” 2007 Symposium on VLSI Technology Digest of Technical Papers, pp. 14-15.

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