Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2002-05-17
2003-12-09
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S205000
Reexamination Certificate
active
06661714
ABSTRACT:
RELATED APPLICATION
This application claims priority to Korean Patent Application No. 2001-38815, filed on Jun. 30, 2001, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices, and more particularly, to semiconductor memory devices having sense amplifiers therein that amplify differential input signals.
BACKGROUND OF THE INVENTION
Semiconductor devices have been continuously developed to increase their capacity and speed and lower their power consumption. To realize low power consumption, a dynamic random access memory (DRAM) device may use a bit-line sense amplifier that is shared by two neighboring memory cell array blocks and an internal memory cell array power supply voltage as a power supply voltage of the shared bit-line sense amplifier. The internal memory cell array power supply voltage is a voltage that is typically reduced from an external power supply voltage. If the internal memory cell array power supply voltage is excessively reduced, the operational features of the bit-line sense amplifier may be degraded.
FIG. 1
shows a memory cell array of a conventional DRAM and
FIG. 2
is a waveform diagram illustrating the operation of a sense amplifier in the conventional DRAM shown in FIG.
1
. Referring to
FIG. 1
, bit-line sense amplifiers S
1
through S
4
are shared by two neighboring memory cell arrays
11
and
13
. Pairs of bit-lines BL
0
i
/BL
0
Bi through BL
3
i
/BL
3
Bi that are connected to a first memory cell array block
11
are initially equalized to a level Vb
1
by equalization circuits E
1
through E
4
, and other pairs of bit-lines BL
0
j
/BL
0
Bj through BL
3
j
/BL
3
Bj that are connected to a second memory cell array block
13
are initially equalized to the level Vb
1
by equalization circuits E
5
through E
8
.
In
FIG. 2
, first and second isolation control signals PISOi and PISOj initially rise to the level of an external power supply voltage Vdd. Thereafter, the first isolation control signal PISOi rises to the level of a boosted voltage Vpp and the second isolation control signal PISOj falls to the level of the ground voltage Vss. As a result, pairs of first isolation transistors T
1
through T
8
are turned on, whereas pairs of second isolation transistors T
9
through T
16
are turned off. That is, the first memory cell array block
111
is selected, but the second memory cell array block
13
is not selected.
Then, a word line WL of a row of memory cells of the first memory cell array
11
reaches the boosted voltage level Vpp, a sense amplifier control signal LAPG reaches logic a “low” level and an inverted sense amplifier control signal LANG rises to a logic “high” level. As a result, sense amplifiers S
1
through S
4
begin to operate. That is, a first switch SW
1
is turned on to provide pull-up current to a power supply voltage node LA of the sense amplifiers S
1
through
54
by connecting the memory cell array power supply voltage V-array to the node LA. A second switch SW
2
is also turned on to provide a ground voltage node LAB with the ground voltage VSS. The sense amplifiers S
1
through S
4
amplify data in the form of differential signals established across the pairs of the bit-lines BL
0
i
/BL
0
Bi through BL
3
i
/BL
3
Bi connected to the first memory cell array block
11
.
However, according to the operation of the sense amplifier shown
FIG. 2
, the pairs of the first isolation transistors T
1
through T
8
are turned on earlier as expected by the first isolation control signal PISOi rising almost to the Vpp level during the initial operation of the sense amplifiers S
1
through S
4
. Thus, a load of the pairs of bit-lines BL
0
i
/BL
0
Bi through BL
3
i
/BL
3
Bi connected to the first memory cell array block II is increased. This increased loading degrades the operational features of the sense amplifiers S
1
through S
4
and, further, reduces amplification speed.
FIG. 3
is a waveform diagram illustrating another operation of the sense amplifier in the conventional DRAM shown in FIG.
1
. Here, the sense amplifier has improved operational features compared to that shown in FIG.
2
. Referring to
FIG. 3
, the first and second isolation control signals PISOi and PISOj initially rise to the external power supply voltage level Vdd. Then, the first isolation control signal PISOi is kept at the outside power supply voltage Vdd level and the second isolation control signal PISOj falls to the ground voltage Vss level during the initial operation of the sense amplifiers S
1
through S
4
. Thereafter, the first isolation control signal PISOi rises to the boosted voltage level Vpp during the middle part of the operation of the sense amplifiers S
1
through S
4
.
According to the operation of the sense amplifier shown
FIG. 3
, the pairs of the first isolation transistors T
1
through T
8
have lower conductivity because the first isolation control signal PISOi has a lower level of Vdd and, therefore, a load on the pairs of the bit-lines BL
0
i
/BL
0
Bi through BL
3
i
/BL
3
Bi connected to the first memory cell array block
11
is decreased. As a result, the amplification speed of the sense amplifiers S
1
through S
4
is increased.
However, if the memory cell array power supply voltage Varray provided to the sense amplifiers S
1
through S
4
is comparatively high, data values which are achieved by sharing charge between a memory cell and bit line cannot be satisfactorily transmitted to the sense amplifiers S
1
through S
4
. To prevent this, the memory cell array power supply voltage Varray must be lowered. However, in this case, the operational features of the sense amplifiers S
1
through S
4
may deteriorate.
SUMMARY OF THE INVENTION
Integrated circuit devices according to embodiments of the present invention provide supplemental pull-up drive currents to one or more sense amplifiers therein during operations (e.g., read operations) to sense and amplify differential signals established across inputs of the sense amplifiers. These additional pull-up drive currents are provided to improve the timing characteristics of the sense amplifiers by making them less susceptible to degraded performance that may be caused by insufficiently high internal voltages.
In particular, first embodiments of the present invention include integrated circuit devices having preferred control circuitry therein. This control circuitry drives a power supply terminal of a differential sense amplifier with a plurality of pull-up drive currents. These pull-up drive currents are derived from a corresponding plurality of signal lines that are each electrically coupled to the power supply terminal of the differential sense amplifier. These signal lines are driven at different positive voltage levels during sense and amplify time intervals (i.e., when the sense amplifier is active).
Additional embodiments of the present invention include integrated circuit memory devices having multiple banks of memory arrays therein. These memory arrays may be coupled to a bank of sense amplifiers, with each sense amplifier having first and second inputs electrically coupled to a pair of differential signal lines. A pull-up control circuit is also provided. The pull-up control circuit provides pull-up drive currents in parallel from first and second voltage supply sources having different magnitudes to a power supply terminal of the sense amplifier when the sense amplifier is amplifying a differential input signal established across the first and second inputs. Memory devices according to this embodiment may also include first and second isolation transistors having first and second gate electrodes electrically coupled to an isolation control signal line. Furthermore, the pull-up control circuit may include a first MOS transistor (e.g., NMOS or PMOS transistor) having a first current carrying terminal (source/drain) electrically coupled to the isolation control signal line and a second current carrying terminal (source/drain) electrically coupled to the power supply terminal of the
Elms Richard
Myers Bigel & Sibley & Sajovec
Nguyen Tuan T.
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