Integrated circuit memory devices having reduced susceptibility

Details Integrated circuit memory devices having reduced susceptibility Integrated circuit memory devices having reduced susceptibility

1996-11-29

1998-03-31

Le, Vu A.

Static information storage and retrieval

Floating gate

Particular connection

36518505, 36518511, 365 63, G11C 1140

Patent

active

057346097

ABSTRACT:
Integrated circuit memory devices having reduced susceptibility to inadvertent programming and erasure include an array of memory cells arranged as a plurality of NAND strings of EEPROM cells which share common control lines (e.g., SSL1, SSL2) and word lines (e.g., WL1-WLn). These NAND strings preferably comprise a linear array or chain of EEPROM cells having first and second ends and first and second select transistors (ST1, ST2) coupled (directly or indirectly) to (he first and second ends, respectively. To provide improved program and erase capability, a pair of NAND strings are provided in antiparallel and share a common bit line. However, the pair of NAND strings are formed in respective nonoverlapping well regions in a substrate so that the channel regions of the EEPROM cells in respective NAND strings can be individually controlled (e.g., raised) to prevent inadvertent programming or erasing when cells in adjacent strings are being programmed or erased, respectively.

REFERENCES:
patent: 5253206 (1993-10-01), Tanaka et al.
patent: 5392238 (1995-02-01), Kirisawa
patent: 5589699 (1996-12-01), Araki

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