Integrated circuit memory devices having improved sense and...

Details Integrated circuit memory devices having improved sense and... Integrated circuit memory devices having improved sense and...

1999-09-21

2001-04-24

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Powering

C365S207000, C365S189090

Reexamination Certificate

active

06222787

ABSTRACT:

RELATED APPLICATION
This application is related to Korean Application No. 98-39814, filed Sep. 24, 1998, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to integrated circuits, and more particularly to integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Increases in the integration levels of integrated circuit memory devices may result in concomitant increases in the power consumption requirements of memory devices. Accordingly, attempts have been made to improve the power consumption efficiency of circuits that make up an integrated circuit memory device. Unfortunately, such attempts to improve power consumption efficiency may cause a reduction in the reliability of highly integrated memory devices.
FIG. 1
is a block diagram of a conventional integrated circuit memory device (e.g., DRAM device). As illustrated, the memory device includes control logic
80
, an internal power supply voltage generator
90
, a row address buffer
10
, a column address buffer
20
, a row decoder
30
, a memory cell array
50
, a sense amplifier
60
, a column decoder
40
, a data input buffer
70
a
and a data output buffer
70
b
. As illustrated by
FIGS. 1-2
, the internal power supply voltage generator
90
generates an internal supply voltage signal AIVC in response to an external supply voltage signal EVC. In particular, the internal power supply voltage generator
90
operates to actively pull up signal line AIVC when signal line PAIVCE is set to a logic 1 level, however, when signal line PAIVCE is set to a logic 0 level, the internal power supply voltage generator
90
does not supply pull-up current to signal line AIVC. The logic 1 pulse width of signal PAIVCE is typically directly related to the active pulse width of the row address strobe signal /RAS. As illustrated by
FIG. 2
, increases in the external supply voltage EVC above a predetermined clamping level (e.g., 2.5 volts) will not result in further corresponding increases in the magnitude of the signal provided to signal line AIVC.
Referring now to
FIG. 3
, an operation to read data from a memory cell within the array
50
includes the step of driving a corresponding word line WL to an active level (i.e., logic 1 level). In response, charge from within the memory cell will be transferred to a corresponding bit line BL and the bit line will rise slightly in potential. If the sense amplifier
60
is active (LANG=1, LAPG=0), the sense amplifier will use current provided by signal line AIVC to amplify and drive the differential bit lines BL and /BL to opposite logic levels, as illustrated. During this amplification operation, the voltage level on signal line AIVC may drop. Moreover, because the internal power supply voltage generator
90
may only operate to actively pull-up signal line AIVC while signal line PAIVCE is at a logic 1 level, the signal line AIVC may not return to a voltage level of 2.5 volts at the time the signal line PAIVCE transitions from 1-0. The reduction is illustrated by the amount “&Dgr;V”. If this happens, the differential bit lines may not be driven to their full rail-to-rail levels and the reliability of data restore operations (when charge is transferred back into the selected memory cells to restore the data therein) may be reduced. This likelihood of reduced reliability may also be increased if the duration of the active row address strobe signal /RAS is decreased to achieve higher frequency of operation. Thus, notwithstanding attempts to develop more highly integrated memory devices, there continues to be a need for memory devices that can be more reliable when operating at relatively low voltage levels and at high frequencies.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved integrated circuit memory devices.
It is another object of the present invention to provide integrated circuit memory devices that can provide highly reliable data reading and data restore operations notwithstanding low voltage and/or high frequency operation.
These and other objects, advantages and features of the present invention can be provided by integrated circuit memory devices that preferably include a control circuit that generates an active first control pulse (e.g., PR) having a first duration, in response to an active strobe pulse (e.g., /RAS) that may be generated during a data reading operation. To allow improved reliability of the data reading operation and any subsequent data restore operation, particularly when the duration of the active strobe pulse is relatively short, a pulse width extension circuit is provided. The pulse width extension circuit converts the active first control pulse into an active second control pulse (e.g., PAIVCE
2
) having a second duration greater than the first duration. This active second control pulse is then provided as a control input to an internal voltage generator. In particular, the internal voltage generator is provided to drive a supply signal line (e.g., AIVC
2
) at a first supply voltage in response to the active second control pulse. The supply signal line may be provided as an internal supply line to one or more active circuits within the memory device.
For example, the supply signal line may be used to power a differential sense amplifier during data reading and data restore operations (i.e., when data is being sensed and amplified on a pair of differential bit lines). According to a preferred aspect of the present invention, these reading and restore operations may be performed with higher reliability if the additional pulse duration provided by the pulse width extension circuit is sufficient to enable a complete recharging of the differential bit lines of the sense amplifier prior to performance of a data restore operation.


REFERENCES:
patent: 4975877 (1990-12-01), Bell
patent: 5014245 (1991-05-01), Muroka et al.
patent: 5592429 (1997-01-01), Hirata
patent: 5640350 (1997-06-01), Iga
patent: 5646565 (1997-07-01), Tukidate
patent: 5694361 (1997-12-01), Uchida
patent: 5793667 (1998-08-01), Schwee

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