Integrated circuit memory devices having data selection circuits

Details Integrated circuit memory devices having data selection circuits Integrated circuit memory devices having data selection circuits

1999-01-22

2000-11-21

Elms, Richard

Static information storage and retrieval

Addressing

Sync/clocking

3652335, 36523004, 3652257, 365194, G11C 800

Patent

active

061512710

ABSTRACT:
Integrated circuit memory devices include first and second memory banks, first and second local data lines electrically coupled to the first and second memory banks, respectively, and a multiplexer having first and second inputs electrically coupled to first and second data bus lines, respectively. A data selection circuit is also provided which routes data from the first and second local data lines to the first and second data bus lines, respectively, when a selection control signal is in a first logic state and routes data from the second and first local data lines to the first and second data bus lines, respectively, when a selection control signal is in a. second logic state opposite the first logic state. A control signal generator is also provided. This control signal generator generates the selection control signal in the first and second logic states when a first address in a string of burst addresses is even and odd, respectively.

REFERENCES:
patent: 4758995 (1988-07-01), Sato
patent: 5844859 (1998-12-01), Iwamoto et al.
patent: 5892730 (2000-01-01), Sato et al.
patent: 6014759 (2000-01-01), Manning
Saeki et al., "SP23.4: A 2.5ns Clock Access 250MHz 256Mb SDRAM With a Synchronous Mirror Delay", ISSCC, 1996, pp. 374-375.

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