Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2007-08-21
2007-08-21
Elms, Richard T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189050, C365S230080
Reexamination Certificate
active
11265475
ABSTRACT:
Memory devices include a memory cell array, a column selection circuit electrically coupled to the memory cell array and a data line driver circuit. The data line driver circuit is configured to drive an output port of the memory device with read data received from the column selection circuit during a read cycle time interval. The data line driver circuit is further configured to support an extended read cycle time interval by switching from a non-latching mode of operation during a leading portion of the read cycle time interval to a latching mode of operation during a trailing portion of the read cycle time interval. The data line driver circuit may include a drive inverter having an output electrically connected to one of a plurality of output pins associated with an output port and a feedback inverter having an input electrically connected to the output of the drive inverter. This feedback inverter may have an output electrically connected to an input of the drive inverter and at least one enable terminal responsive to a data line latch signal. The latching mode of operation may be commenced in response to a leading edge of the data line latch signal.
REFERENCES:
patent: 6947348 (2005-09-01), Kim et al.
patent: 10-1996-035671 (1998-05-01), None
patent: 10-1997-000665 (1998-10-01), None
patent: 10-2004-0048745 (2004-06-01), None
Elms Richard T.
Myers Bigel & Sibley Sajovec, PA
Nguyen N
Samsung Electronics Co,. Ltd.
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