Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-07-17
2002-04-16
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030, C365S189110, C365S240000
Reexamination Certificate
active
06373757
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly to integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Highly integrated circuit memory devices frequently include redundant memory blocks therein that can be substituted for defective memory blocks. One conventional method of replacing a defective block of memory with a redundant block of memory utilizes a shift column redundancy scheme. In a typical shift column redundancy scheme, an input/output (IO) line corresponding to the defective block of memory is disabled, and the other IO lines associated with the other blocks of memory as well as the IO line associated with the redundant block of memory are “shifted” down and enabled as functional IO lines. Unfortunately, merely disabling an IO line associated with a defective block of memory may not entirely isolate the defective block of memory from influencing the operation of the memory device. For example, if one or more bit lines within a defective block of memory are defective as a result of processing defects, then electrical “shorts” may be present between one or more bit lines and a ground reference potential. These shorts may significantly increase the power consumption of the memory device if the defective bit lines become biased at a positive reference potential (e.g., Vdd).
To address this problem, memory devices have been designed to include fuses in the pull-up paths associated with the bit lines. For example, U.S. Pat. No. 5,390,150 to Kwak et al., entitled “Semiconductor Memory Device with Redundancy Structure Suppressing Power Consumption”, describes the use of fuses to reduce power consumption requirements. U.S. Pat. No. 5,768,206 to McClure, entitled “Circuit and Method for Biasing Bit Lines”, also discloses the use of a fuse to selectively disable the pull-up path associated with a pair of bit lines when the bit lines are within a defective block of memory. Unfortunately, such devices may require the use of an unnecessarily large number of fuses to provide significant power reduction. The use of a large number of fuses may also limit the integration density of a memory device. Thus, notwithstanding these attempts, there continues to be a need for more highly integrated memory devices having reduced power consumption requirements in the presence of bit line shorts and other processing errors.
SUMMARY OF THE INVENTION
Preferred memory devices of the present invention comprise a first bit line within a first block of memory and a second bit line within a second block of memory. The first bit line is electrically coupled to a reference voltage signal line (e.g., Vdd, ½Vdd) by a pull-up transistor (e.g., PMOS transistor) that turns on in response to an active first bit line pull-up signal (e.g., /BLPU_IOn=0). The second bit line is also electrically coupled to the reference voltage signal line by a pull-up transistor that turns on in response to an active second bit line pull-up signal (e.g., /BLPU_IOn+1=0). A preferred control circuit is also provided and this control circuit is responsive to a multi-bit shift signal. The control circuit disables generation of the active first bit line pull-up signal in favor of an active second bit line pull-up signal when a value of the shift signal designates replacement of the first block of memory with the second block of memory.
A preferred control circuit comprises a shift redundancy control circuit, which generates a plurality of bit line select signals (e.g., SEL and /SEL) in response to the shift signal, and a bit line pull-up control circuit that is responsive to the plurality of bit line select signals. The bit line pull-up control circuit preferably generates the inactive first bit line pull-up signal and the active second bit line pull-up signal if a value of the plurality of bit line select signals designates replacement of the first block of memory with the second block of memory. An input/output routing circuit is also provided for routing data to and from an input/output bus and multiple blocks of memory, including a redundant block. This routing circuit is electrically coupled to all the blocks of memory and is responsive to the plurality of bit line select signals. In particular, the bit line select signals are used by the routing circuit to connect a plurality of memory-side ports to a reduced number of bus-side ports. Accordingly, the same signal that can be used to disable the bit lines in a defective block of memory, can also be used to control the routing circuit and thereby isolate additional devices (e.g., column multiplexers) within a defective block of memory from the bus-side ports.
According to other aspects of preferred embodiments, the shift redundancy control circuit comprises a first plurality of NAND gates having respective first inputs that receive respective bits of the multi-bit shift signal. The redundancy control circuit may also comprise a plurality of first inverters, with each of the first inverters having an input electrically coupled to an output of a respective NAND gate in the first plurality of NAND gates and an output electrically coupled to a second input of a respective NAND gate in the first plurality of NAND gates. The bit line pull-up control circuit may also comprise a second plurality of NAND gates, with each of the second plurality of NAND gates having first and second inputs electrically coupled to the second input and the output, respectively, of a respective NAND gate in the first plurality of NAND gates. In addition, the bit line pull-up control circuit may comprise a third plurality of NAND gates, with each of the third plurality of NAND gates having a first input electrically coupled to an output of a respective NAND gate in the second plurality of NAND gates and a second input that receives a bit line pull-up bank signal (e.g., BLPUBANK). An output of one of the third plurality of NAND gates is electrically connected to bit line pull-up transistors in a respective block of memory and an output of another of the third plurality of NAND gates is electrically connected to bit line pull-up transistors in another block of memory. In this manner, the bit line pull-up control circuit can be used to disable the bit line pull-up transistors in a block of “defective” memory and thereby prevent excessive power consumption that may occur if one or more defective bit lines therein is shorted to a ground or other reference potential, for example. Conventional techniques of reducing power consumption in defective memory blocks by blowing a relatively large number of fuses connected between a power supply potential and each of a plurality of bit lines can therefore be avoided.
Preferred embodiments of the present invention may also include methods of operating an integrated circuit memory device by decoding a first signal and disabling circuitry that controls pull-up of bit lines in a first block of memory if a decoded first signal designates replacement of the first block with another block. Additional methods may also include decoding a multi-bit shift signal as a first bit line control signal having a first logic state if a first block of memory is to be replaced by a second block of memory and generating an inactive bit line pull-up signal that disposes each of the bit lines in the first block of memory in a respective floating state if the first bit line control signal is in the first logic state.
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patent: 6011742 (2000-01-01), Zheng
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Integrated Device Technology Inc.
Le Vu A.
Myers Bigel & Sibley & Sajovec
Nguyen Juan T.
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