Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
1999-12-17
2001-07-03
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S230030, C365S230080
Reexamination Certificate
active
06256218
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and, more particularly, to integrated circuit memory devices.
BACKGROUND OF THE INVENTION
A dynamic random access memory (DRAM) is a type of integrated circuit device. High speed integrated circuit devices are often used, for example, in signal processing applications where conventional DRAM access speeds may be insufficient. High speed integrated circuit memory devices typically input and output data in-synchronization with an externally applied clock signal. For example, in a high speed integrated circuit memory device, data input and output operations may utilize an internal input and output clock signal. Recently, however, in order to achieve high speed operations and/or other advantages, other types of integrated circuit memory devices have been provided. Examples of such memory devices include a fast page mode DRAM, an extended data output (EDO) DRAM, a synchronous DRAM, a double data rate (DDR) DRAM, and a Rambus DRAM have been developed. The operating speed of the memory device is generally increased under various conditions with each of the above DRAMs by increasing the amount of input and output data (bandwidth) accessed per unit time.
Rambus DRAM technology is marketed by Rambus, Inc., Mountain View, Calif. The Rambus technology is described in U.S. Pat. No. 5,473,575 to Farmwald et al., U.S. Pat. No. 5,578,940 to Dillon et al., U.S. Pat. No. 5,606,717 to Farmwald et al. and U.S. Pat. No. 5,663,661 to Dillon et al. A device embodying the Rambus technology is also referred to as a “packet type integrated circuit device”, because each integrated circuit receives data and addresses in packet units.
An example of a conventional Rambus DRAM integrated circuit device is illustrated in FIG.
1
. As shown in
FIG. 1
, the Rambus memory device
101
includes first memory bank
181
and a second memory bank
182
. It also includes a first input and output shift block
111
, a second input and output shift block
112
, an interface logic unit
121
, a first input and output buffer
131
, a second input and output buffer
132
, a delay locked loop circuit
141
and a pad block
151
.
In the conventional Rambus memory device
101
, the first and second input and output buffers
131
,
132
are located in the integrated circuit device substrate displaced (isolated) from the first and second input and output shift blocks
111
,
112
. Typically, the distance between each of the first and second input and output buffers
131
,
132
and the first input and output shift block
111
is about 1000 micrometers (&mgr;m) to 4000 &mgr;m. The distance between each of the first and second input and output buffers
131
,
132
and the second input and output shift block
112
is also typically about 1000 &mgr;m to 4000 &mgr;m. Accordingly, the output drivers (not shown) of the first and second input buffers included, respectively, in the first and second input and output buffers
131
,
132
generally are designed so as to be able to transmit data from the respective first and second input buffers to the corresponding first and second input shift blocks included in the first and second input and output shift blocks
111
,
112
. The output drivers (not shown) of the first and second output shift blocks included in the first and second input and output shift blocks
111
,
112
are also typically designed to have the capability to transmit data from the first and second output shift blocks to the corresponding first and second output buffers included in the first and second input and output buffers
131
,
132
.
As a result of the distances that the drivers are required to support, an undesirably large amount of power is typically consumed by the first and second input buffers and the first and second output shift blocks. In addition, as a result of the length of the data lines
171
-
174
used for data transmission between the first and second input and output buffers
131
,
132
and the first and second input and output shift blocks
111
,
112
, data may be affected by noise.
In a further aspect of the conventional Rambus DRAM illustrated in
FIG. 1
, the delay locked loop circuit
141
generates an input control clock signal (sclk) and an output control clock signal (tclk). The input control clock signal (sclk) controls the input buffers included in the first and second input and output buffers
131
,
132
and the input shift circuits included in the first and second input and output shift blocks
111
,
112
. The output control clock signal (tclk) controls the output buffers included in the first and second input and output buffers
131
,
132
and the output shift circuits included in the first and second input and output shift blocks
111
,
112
. Respective clock lines
161
-
166
provide the input and output control clock signals (sclk) and (tclk) to the first and second input and output buffers
131
,
132
and the first and second input and output shift blocks
111
,
112
The clock lines
161
-
166
are placed in three pairs adjacent to the first and second input and output buffers
131
,
132
, the first input and output shift block
111
, and the second input and output shift block
112
respectively.
As a result of the number of clock lines, the loads on the output drivers of the delay locked loop circuit
141
which drives the clock lines
161
-
166
are typically increased. This loading, in turn typically causes the delay locked loop circuit
141
to consume an increasing amount of power and may require a greater amount of area in the integrated circuit device. Correspondingly, the Rambus memory device
101
also may require a greater amount of area to implement resulting in a larger device.
As shown in
FIG. 1
, the clock lines
165
and
166
are installed between particular pads among a plurality of pads included in the pad block
151
. As a result, a significant amount of noise may be generated in the input and output control clock signals (sclk) and (tclk), passing between the particular pads, due to interference caused by signals applied to the particular pads in the proximity of the clock lines
165
,
166
.
The data lines
173
and
174
for transmitting data between the first and second input and output buffers
131
,
132
and the second input and output shift block
112
are positioned with a portion passing through the pad block
151
as a result of the placement of the pad block
151
between the circuits being connected by the data lines
173
,
174
. This layout may also contribute to increasing the size of the Rambus memory device. In addition, as with the clock signals, signals transmitted via the data lines
173
,
174
may be subjected to interference from signals applied to pads included in the pad block
151
in the vicinity of the data lines
173
,
174
. This noise could lead to instability on the data lines
173
,
174
.
Accordingly, there is a need for improved integrated circuit memory devices such as Rambus DRAMs.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide integrated circuit memory devices which may consume less power.
It is a further object of the present invention to provide integrated circuit memory devices which may be less susceptible generation of noise on clock lines of the integrated circuit memory device.
These and other objects may be provided by integrated circuit memory devices which include input buffers placed adjacent an associated input shift block rather than displaced with intervening regions, such as a pad block, between the buffer and the shift block. As a result, a single input clock line may be provided which can support both the input buffers and the shift block. The single line may also provide less loading allowing a lower power driver in the memory device's clock circuit. In addition, the input clock line may avoid routing through the pad block which in turn may reduce noise on the input clock line from signals in the pad block. The output buffers and associated shift block may also be lo
Lam David
Myers Bigel & Sibley & Sajovec
Nelms David
Samsung Electronics Co,. Ltd.
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