Integrated circuit memory devices and methods including programm

Static information storage and retrieval – Addressing – Plural blocks or banks

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Details

3652257, 365200, G11C 800

Patent

active

057577161

ABSTRACT:
Programmable disabling and selection circuits operate on a block level for integrated circuit memory devices. Thus, a redundant block can be substituted for a block having more defective rows and/or columns than the number of redundant rows and/or columns which are provided in the integrated circuit memory devices. A plurality of normal block selection circuits are included, a respective one of which produces a respective normal block selection signal in response to an address of a respective one of the plurality of blocks of memory cells. A plurality of programmable block selection circuits are also included, a respective one of which is connected between the respective one of the plurality of normal block selection circuits and a respective one of the plurality of blocks of memory cells. Each programmable block selection circuit includes a first fuse, the activation of which blocks the corresponding one of the plurality of normal block selection circuits. Each of the programmable block selection circuits further includes a plurality of second fuses, the activation of which generates a replacement address for the corresponding one of the plurality of blocks of memory cells. A plurality of block disable circuits are also included, a respective one of which is connected to a respective one of the plurality of blocks of memory cells. Each of the plurality of block disable circuits includes a fuse, the activation of which disables the corresponding one of the plurality of blocks of memory cells.

REFERENCES:
patent: 5471431 (1995-11-01), McClure
patent: 5526317 (1996-06-01), McClure
patent: 5548225 (1996-08-01), Roundtree et al.
patent: 5576999 (1996-11-01), Kim et al.

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