Integrated circuit memory device with redundant rows

Details Integrated circuit memory device with redundant rows Integrated circuit memory device with redundant rows

1991-07-17

1994-03-22

Mullins, James B.

Static information storage and retrieval

Read/write circuit

Differential sensing

365214, G11C 702

Patent

active

052970949

ABSTRACT:
A dual-port memory device is provided which has a memory array divided approximately in half. The bit lines for the array are crossed over between array halves in order to minimize stray capacitance and cross-coupling capacitance for the device. Redundant rows are provided for the device which can be programmed to substitute for array rows containing non-functional bits. Preferably, the redundant rows are provided only in one-half of the array. The redundant rows can all be located in a first half of the array, with the second half of the array being the half which provides inverted data for one of the ports. If a redundant row replaces an array row in the second half of the array, and is written to by the port which reads and writes inverted data, the data must be reinverted prior to writing it to, or reading it from, the redundant row.

REFERENCES:
patent: 3942164 (1976-03-01), Dunn
patent: 4630241 (1986-12-01), Kobayashi et al.
patent: 4870619 (1989-09-01), Van Ness

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