Integrated circuit memory device with balancing circuit includin

Details Integrated circuit memory device with balancing circuit includin Integrated circuit memory device with balancing circuit includin

1995-06-07

1996-08-06

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Complementing/balancing

365203, 365208, 365210, 36518521, 36518525, 327 53, 327 54, 327 56, G11C 700

Patent

active

055441149

ABSTRACT:
In reading circuits for memories in integrated circuit form, notably non-volatile memories, to obtain a better compromise between reading speed and the reliability of the information read, there is proposed a reading circuit constituted as follows: a differential amplifier, means for the precharging of the bit line before a reading phase and means for the balancing of the input potentials of the differential amplifier before the reading phase. The balancing means comprise a follower amplifier that has one input connected to the output of the differential amplifier and is connected during the balancing phase in such a way that it injects a load current of the bit line in a direction tending to cancel the output voltage to the differential amplifier. A cascode transistor can be used to accelerate the reading.

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IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, New York, US, pp. 1150-1156, Gastaldi et al., "A 1-Mbit CMOS EPROM with Enhnaced Verification".

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