Integrated circuit memory device with balancing circuit includin

Details Integrated circuit memory device with balancing circuit includin Integrated circuit memory device with balancing circuit includin

1993-07-23

1996-12-03

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Complementing/balancing

365207, 365203, 36518907, 365210, 327 53, 327 54, 327 56, G11C 700

Patent

active

055815111

ABSTRACT:
In reading circuits for memories in integrated circuit form, notably non-volatile memories, to obtain a better compromise between reading speed and the reliability of the information read, there is proposed a reading circuit. A differential amplifier for reading a memory cell is connected to a precharged bit line and reference line. A follower amplifier balances the input potentials of the differential amplifier before the reading phase. The follower amplifier has one input connected to the output of the differential amplifier and is connected during the balancing phase in such a way that it injects a load current to the- bit line in a direction tending to cancel the output voltage of the differential amplifier. A cascode transistor can be used to accelerate the reading.

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IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, New York, US, pp. 1150-1156, Gastaldi et al., "A 1-Mbit CMOS EPROM with Enhanced Verification".

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