Integrated circuit memory device with balancing circuit includin

Details Integrated circuit memory device with balancing circuit includin Integrated circuit memory device with balancing circuit includin

1995-06-07

1997-06-10

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Complementing/balancing

365207, 365210, 327 54, 327 56, G11C 700

Patent

active

056383320

ABSTRACT:
In reading circuits for memories in integrated circuit form, notably non-volatile memories, a differential amplifier for reading the memory cell is connected to a precharged bit line and a reference line. A balancing device balances the potentials of the bit line and reference line, and the corresponding inputs to the differential amplifier, before the reading phase of the circuit. The balancing device includes a follower amplifier having an input connected to the differential amplifier and an output connected to the bit line to inject a load current to the bit line during a balancing phase of the reading circuit.

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IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, New York, US, pp. 1150-1156, Gastaldi et al., "A 1-Mbit CMOS EPROM with Enhanced Verification".

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