Integrated circuit memory device having flash clear

Details Integrated circuit memory device having flash clear Integrated circuit memory device having flash clear

1991-07-17

1994-05-10

Zazworsky, John

Static information storage and retrieval

Addressing

Multiple port access

365 69, 365206, 365900, G11C 800, G11C 702, G11C 506

Patent

active

053114779

ABSTRACT:
A dual-port memory device provides bit lines having a crossover pattern to reduce stray end coupling capacitances. Such crossover occurs approximately in the middle of the memory array for the device. Data in one-half of the array is stored in an inverted manner from data in the other half of the array. A preferred technique for clearing a memory provides for resetting only a portion of the bits of the array for each entry, with the bits of all memory entries being reset simultaneously. In order to provide such a reset function with the preferred bit line crossover scheme, a voltage node used for reset must also provide signal lines which are crossed over in the middle of the array.

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patent: 5144583 (1992-09-01), Oowaki et al.
patent: 5148400 (1992-09-01), Fujii

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