Static information storage and retrieval – Read/write circuit – Testing
Patent
1997-10-02
1999-07-20
Nelms, David
Static information storage and retrieval
Read/write circuit
Testing
36518521, 365200, 365205, 36523003, G11C 700
Patent
active
059264225
ABSTRACT:
An integrated circuit memory device (10) has a current-mode data compression test mode. The memory device (10) includes a memory array having a plurality of sub-arrays (12) of memory cells. The memory cells are selected for read operations by Y-select lines (18) and word lines (16). Selected memory cells are coupled to main amplifier circuits (28) via bit lines (14), sense amplifiers (20), sub-input/output lines (22), sub-amplifier circuits (24), and main input/output lines (26). Each main amplifier circuit (28) is operable, during a normal read operation, to provide a data output (DOUT) representing a data state of a selected memory cell. During a test mode read operation, each main amplifier circuit (28) is operable to provide a data output (DOUT) representing a data state of a plurality of selected memory cells if the plurality of selected memory cells have the same data state, and to provide an error signal (ERROR) if the plurality of selected memory cells have different data states. The test mode read operation is characterized by activating a Y-select line (18) and a plurality of word lines (16) to select a plurality of memory cells that are coupled to different sub-amplifier circuits (24) that feed the same main amplifier circuit (28).
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Donaldson Richard L.
Hoel Carlton H.
Holland Robby T.
Nelms David
Nguyen Tuan T.
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