Integrated circuit memory device having built-in self test circu

Details Integrated circuit memory device having built-in self test circu Integrated circuit memory device having built-in self test circu

1997-11-14

1999-08-10

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

36523008, 365191, 36518905, G11C 700

Patent

active

059369000

ABSTRACT:
An integrated circuit memory device (10) is provided that has a self test monitor mode. The memory device (10) includes a memory array (26) having a plurality of memory cells. The memory device (10) further includes a built-in self test circuit (12) connected to receive a self test select signal. The built-in self test circuit (12) is operable, when the memory device (10) is in self test mode, to generate internal self test signals for operating and testing the memory array (26). A data buffer (28) is connected to receive the internal self test signals and a monitor mode signal. The data buffer (28) is operable, when the memory device (10) is in self test monitor mode, to connect the internal self test signals to terminals of the memory device (10) to provide the internal self test signals externally from the memory device (10). The monitored internal self test signals can be used to verify operation of the built-in self test circuit (12). The monitored self test signals can also be used in a tester mode to test other memory devices.

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