Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-12-03
2001-06-19
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S103000, C711S104000, C257S296000, C257S298000, C365S063000
Reexamination Certificate
active
06249841
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit (“IC”) memory devices. More particularly, the present invention relates to an integrated circuit memory device employing multiple non-volatile memory technologies integrated on a common substrate, specifically, Flash and ferroelectric random access memory cells and wherein certain of the disadvantages inherent in the former are ameliorated by its combination with the latter.
Various types of non-volatile memory devices are currently available, by means of which data can be retained without the necessity of a continuously applied power source. These include, for example, erasable programmable read only memory (“EPROM”) devices, including electrically erasable (“EEPROM”) devices, and Flash memory. Flash memory cells are generally similar in construction to that of an EPROM cell with the exception that they incorporate a relatively shallower gate oxide thickness of on the order of 10-20 nanometers (to allow Fowler-Nordheim electron tunneling) and the fact that erase operations must be done either in blocks or over the entire memory chip at once. Functionally, the contents of Flash, EPROM and EEPROM memory devices must all be erased prior to being written with new data.
The confluence of its relatively low cost and programmability features has established Flash memory as the currently dominant non-volatile memory technology. With a comparatively small memory cell structure and the capability of field programmability, it is generally superior to the other floating gate technologies from which it is derived. Nevertheless, programming (or writing) Flash memory is particularly difficult and time consuming resulting in a relatively slow access time, particularly with respect to “write” operations.
As mentioned previously, a Flash memory device must be erased prior to writing and to this end, recent devices have partitioned the memory array into sectors such that only a portion of the memory need be erased to write to a given sector. This then allows the user to read other portions of the memory after one sector is erased, with erasure of a typical Flash memory sector requiring between one and fifteen seconds. During this time period, it is difficult to access a Flash memory so still other Flash memory devices now allow the erase process to be momentarily interrupted to perform a “read” operation. Nevertheless, no current devices will permit a “write” during the erase cycle.
Still another disadvantage of Flash memories is that they are relatively slow to program. That is, even after erasure, a byte of Flash memory typically requires between 9 and 300 microseconds to program. For example, a 4Mb Flash memory device divided into sectors may exhibit a maximum sector size of 512 Kb or 64 Kbytes. The programming time for an entire sector would then require somewhere between 576 and 19.2K microseconds. While the programming of a Flash memory is still relatively faster than its preceding erase cycle, it is still very slow in terms of central processing unit (“CPU”) speed and hinders overall system input/output (“I/O”) performance.
In contrast to Flash memory technology, ferroelectric memory devices, such as the FRAME® (a registered trademark of Ramtron International Corporation, Colorado Springs, Colorado) family of solid state, random access memory integrated circuits provide non-volatile data storage through the use of a ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within the Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field which exceeds the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles.
Data stored in a ferroelectric memory cell is “read” by applying an electric field to the cell capacitor. If the field is applied in a direction to switch the internal dipoles, more charge will be moved than if the dipoles are not reversed. As a result, sense amplifiers can measure the charge applied to the cell bit lines and produce wither a logic “1” or “0” at the IC output pins. In a conventional two transistor/two capacitor (“2C/2T”) ferroelectric memory cell, (one transistor/one capacitor “1T/1C” devices have also been described) a pair of two data storage elements are utilized, each polarized in opposite directions. To “read” the state of a 2T/2C memory cell, both elements are polarized in the same direction and the sense amps measure the difference
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between the amount of charge transferred from the cells to a pair of complementary bit lines. In either case, since a “read” to a ferroelectric memory is a destructive operation, the correct data is then restored to the cell during a precharge operation.
In a simple “write” operation, an electric field is applied to the cell capacitor to polarize it to the desired state. Briefly, the conventional write mechanism for a 2T/2C memory cell includes inverting the dipoles on one cell capacitor and holding the electrode, or plate, to a positive potential greater than the coercive voltage for a nominal 100 nanosecond (“nsec.”) time period. The electrode is then brought back to circuit ground for the other cell capacitor to be written for an additional nominal 100 nsec.
As can be seen, ferroelectric memory technology is vastly superior to Flash memory in terms of its programming time and device complexity. However, Flash memory has a current market penetration that ferroelectric technology has not yet achieved.
SUMMARY OF THE INVENTION
The device and method of the present invention advantageously discloses the combination of both Flash and ferroelectric memory technologies on a common substrate in a manner that allows a relatively small amount of ferroelectric random access memory to mitigate many of the disadvantages exhibited by current Flash technology devices. In particular, whether combined together as a single stand-alone memory device or embedded together as a portion of a processor, microcontroller or application specific integrated circuit (“ASIC”) a block of ferroelectric memory that is sized to match the largest individually erasable sector of Flash memory can effectively compensate for the latter's slow erasure and write times.
The utility of the present invention is exemplified by a representative 4Mb Flash memory device with a maximum sector size of 512 Kb which may be integrated with a 512 Kb block of ferroelectric memory. Depending on the particular application intended, various combinations of hardware and software may then be utilized to dynamically map the ferroelectric memory block to any erased sector of the Flash memory array. Particular advantages inure by combining the Flash and ferroelectric memories on a common substrate with the provision of the requisite interface circuitry to enable automatic operation.
Particularly disclosed herein is an integrated circuit memory device comprising a non-volatile memory block comprising at least one memory sector and a ferroelectric memory block integrated on a common substrate with the non-volatile memory block, the ferroelectric memory block being configured to maintain data intended to be written to the at least one memory sector while an erase operation is performed thereon.
Also disclosed herein is an integrated circuit device comprising a processor; a non-volatile memory block integrated on a common substrate with the processor, the non-volatile memory block comprising at least one memory sector; and a ferroelectric memory block integrated on a common substrate with the processor and the non-volatile memory block, the ferroelectric memory block being configured to maintain data intended to be written to the at least one memory sector while an erase operation is performed thereon.
Still further disclosed herein is a method
Alwais Michael
Carrigan Donald G.
Sikes L. David
Elmore Reba I.
Hogan & Hartson LLP
Kubida William J.
Ramtron International Corporation
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