Integrated circuit, memory chip and method of evaluating a...

Details Integrated circuit, memory chip and method of evaluating a... Integrated circuit, memory chip and method of evaluating a...

2007-01-12

2008-07-15

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Systems using particular element

Resistive

C365S210130

Reexamination Certificate

active

07400521

ABSTRACT:
An integrated circuit comprises a resistive memory cell, at least one reference cell, a first device configured to apply a predetermined read voltage to the resistive memory cell and a second device configured to apply the predetermined read voltage to the reference cell. The resistive memory cell can be switched between a highly resistive memory state and at least one lowly resistive memory state. The reference cell comprises a resistance value representing a reference state. The first device generates the read voltage for a first resistance range, the first resistance range comprising the memory states of the resistive memory cell. The second device generates the read voltage for a second resistance range, the second resistance range being smaller in comparison to the first resistance range and comprising the reference state of the reference cell.

REFERENCES:
patent: 5828616 (1998-10-01), Bauer et al.
patent: 6597598 (2003-07-01), Tran et al.
patent: 7009881 (2006-03-01), Noguchi
patent: 2005/0276091 (2005-12-01), Inoue
patent: 2006/0239066 (2006-10-01), Liaw
patent: 2007/0165442 (2007-07-01), Hosoi et al.
patent: 2008/0043521 (2008-02-01), Liaw et al.

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