Integrated circuit memory cells and methods of forming

Details Integrated circuit memory cells and methods of forming Integrated circuit memory cells and methods of forming

2004-09-01

2008-11-18

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S302000, C257S306000, C257S334000, C257S401000, C257S773000

Reexamination Certificate

active

07453112

ABSTRACT:
An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor dielectric between the first and second electrodes, and a vertical transistor above and including the first source/drain. The second source/drain may be included in a digit line inner conductor connecting a digit line to a transistor channel of the vertical transistor. The channel may include a semiconductive upward extension of the combined first electrode and first source/drain. The memory cell may be included in an array of a plurality of such memory cells wherein the second electrode is a common electrode among the plurality. The memory cell may provide a straight-line conductive path between the first electrode and a digit line, the path extending through the vertical transistor.

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