Integrated circuit manufacturing method using hard mask

Details Integrated circuit manufacturing method using hard mask Integrated circuit manufacturing method using hard mask

2007-04-24

2009-11-10

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S638000, C438S672000, C438S624000, C438S508000

Reexamination Certificate

active

07615484

ABSTRACT:
An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.

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patent: 6992003 (2006-01-01), Spencer et al.
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patent: 2005/0233584 (2005-10-01), Jeon et al.
patent: 2007/0264820 (2007-11-01), Liu et al.

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