Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-09-19
2003-02-25
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06526554
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an integrated circuit layout system, an integrated circuit layout method, and a computer-readable storage medium storing a program therefor in which dummy gates can be appropriately arranged on a semiconductor chip.
2. Description of the Related Art
Recently, the development of technologies for fine semiconductor integrated circuits has paved the way for large-scale integrated circuits. However, this involves a number of cases where various defects of the semiconductor integrated circuit are found after a diffusion step and the like of the manufacturing process, which can not be found at design step. The occurrence of such post-design defects has required a redesign for the most part, leading to protracted development TAT (Turn Around Time).
To cope with such a problem, a technique of arranging dummy gates into an integrated circuit at the point of layout has been recently adopted to minimize redesigns. Dummy gates mean predetermined gates which are unused at the point of initial design and can be effectively used on correction.
More specifically, when post-design defects occur, dummy gates arranged in the integrated circuit can be used to redesign (rewire) the connections and the like of those correction-requiring portions alone, so as to reduce the development TAT.
Hereinafter, a conventional layout method of arranging dummy gates in an integrated circuit will be described with reference to the drawings.
FIG. 1
is a flowchart showing conventional layout processing.
FIG. 2
is a schematic diagram showing a conventional netlist having dummy gates inserted therein.
FIG. 3
is a schematic diagram showing dummy gates being arranged irregularly within individual modules on a semiconductor chip with in-module divisions.
Initially, a netlist including dummy gates is generated (step S
101
). The netlist generated here has, for example, a hierarchical structure as shown in FIG.
2
. This netlist includes divided target modules
2
B,
2
C, and
3
A at different levels, and dummy gates g
11
-g
13
associated with the same.
Then, the presence or absence of a floor plan is determined (step S
102
). If a floor plan is needed, module divisions are made (step S
103
) and grouping is performed (step S
104
).
Then, modules are arranged on a predetermined semiconductor chip (step S
105
). For example, as shown in
FIG. 3
, the individual modules included in the netlist are arranged at their predetermined positions on a semiconductor chip T
11
.
Finally, inter-module connections and other wiring are installed (step S
106
) to end the layout processing.
Such conventional layout processing, however, disposed dummy gates at random depending on the order of description in the netlist, the algorithm of the layout tool, and the like. As shown by black circles in
FIG. 3
, dummy gates dg were therefore scattered or concentrated over the target modules
2
B,
2
C, and
3
A on the semiconductor chip T
11
, being far from uniform arrangement.
When the dummy gates dg were thus arranged at random on the semiconductor chip T
11
, it was sometimes impossible for these dummy gates dg to be used for logic changes since no available dummy gate dg existed within the area of allowable delays and the like, or no available dummy gate was in fan-out specifications.
That is, in such cases, the modification using dummy gates dg was impossible. This necessitated a redesign of the most part, resulting in a problem of precluding a reduction of development TAT.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an integrated circuit layout system, an integrated circuit layout method, and a computer-readable storage medium storing a program therefor which make it possible to arrange dummy gates uniformly on a semiconductor chip for the reduction of development TAT.
A first aspect of an integrated circuit layout system according to the present invention comprises: dummy gate inserting unit for inserting dummy gate information into a netlist defining connections of circuit elements constituting an integrated circuit; dummy gate distributing unit for distributing a predetermined number of dummy gates to modules in accordance with the netlist having dummy gate information inserted therein by the dummy gate inserting unit; and dummy gate arranging unit for arranging the individual dummy gates distributed by the dummy gate distributing unit uniformly within respective module areas on a chip.
In the present invention, the dummy gate inserting unit inserts dummy gate information into a netlist which defines connections of circuit elements constituting an integrated circuit. The dummy gate distributing unit distributes a predetermined number of dummy gates to modules in accordance with the netlist having the dummy gate information inserted therein by the dummy gate inserting unit. Then, the dummy gate arranging unit arranges the individual dummy gates distributed by the dummy gate distributing unit uniformly within respective module areas on a chip. Accordingly, even when post-design defects occur, the dummy gates can be effectively used to redesign the connections and the like of those correction-requiring portions alone, within the areas of allowable delays and the like or within fan-out specifications. This allows a reduction in development TAT.
A second aspect of an integrated circuit layout system according to the present invention comprises: dummy gate inserting unit for inserting dummy gate information into a netlist defining connections of circuit elements constituting an integrated circuit; area designating unit for designating a plurality of areas on a chip to arrange circuit elements in accordance with the netlist having dummy gate information inserted therein by the dummy gate inserting unit; dummy gate distributing unit for distributing a predetermined number of dummy gates to the areas designated by the area designating unit; and dummy gate arranging unit for arranging the individual dummy gates distributed by the dummy gate distributing unit uniformly within the respective areas on the chip.
In the present invention, the dummy gate inserting unit inserts dummy gate information into a netlist which defines connections of circuit elements constituting an integrated circuit. The area designating unit designates a plurality of areas on a chip to arrange circuit elements in accordance with the netlist having the dummy gate information inserted therein by the dummy gate inserting unit. Then, the dummy gate distributing unit distributes a predetermined number of dummy gates to the areas designated by the area designating unit. The dummy gate arranging unit arranges the individual dummy gates distributed by the dummy gate distributing unit uniformly within the respective areas on the chip. Accordingly, even when post-design defects occur, the dummy gates can be effectively used to redesign the connections and the like of those correction-requiring portions alone, within the areas of allowable delays and the like or within fan-out specifications. This allows a reduction in development TAT.
In this invention, the dummy gate inserting unit may insert, for example, dummy gate information including at least the total number of dummy gates into the top level of a hierarchical netlist which defines connections of circuit elements constituting an integrated circuit. The dummy gate distributing unit may distribute all the dummy gates included in the dummy gate information in accordance with the number of circuit elements targeted for the distribution.
A first aspect of an integrated circuit layout method according to the present invention comprises: inserting dummy gate information into a netlist defining connections of circuit elements constituting an integrated circuit; distributing a predetermined number of dummy gates to modules in accordance with the netlist having dummy gate information inserted therein; and arranging the individual dummy gates distributed uniformly within respective module areas on a chip.
In the present i
Foley & Lardner
Levin Naum
Smith Matthew
LandOfFree
Integrated circuit layout system, integrated circuit layout... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit layout system, integrated circuit layout..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit layout system, integrated circuit layout... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3152854